搜索资源列表
uart8.zip
- 使用Libero提供的异步通信IP核实现UART通信，并附带仿真程序。UART设置为1位开始位，8位数据位，1位停止位，无校验。且UART发送自带2级FIFO缓冲，占用FPGA面积很小。,Libero provided the use of asynchronous communication IP core implementation UART communications, and incidental simulation program. UART is set to 1 to sta
tetrix_vhdl
- 使用vhdl实现的俄罗斯方块，包含mds图和源代码-Tetris using vhdl implementation, including diagrams and source code mds
FPGA-LDPC
- 用FPGA实现使用LDPC编码器和译码器-FPGA implementation by using LDPC encoder and decoder
cpu
- cpu的vhdl设计实现加法减法乘法运算-cpu VHDL Design and Implementation of multiplication addition subtraction
20090224fpga
- 《数字信号处理的FPGA实现》代码，数字信号处理一些算法的FPGA代码，比较全-" Digital signal processing FPGA implementation" code, digital signal processing FPGA code some algorithms to compare the whole
NCO
- 基于FPGA和SRAM的数控振荡器的设计与实现-SRAM-based FPGA and NCO of the design and implementation
fft
- an fft implementation help
Viterbi
- Viterbi译码器的FPGA实现代码,来在国外大学论坛.-Viterbi decoder implementation of the FPGA code to the Forum at foreign universities.
studyFFTcore
- 调用FPGA的IP核实现FFT运算，在xilinx的vertex4sx55FPGA的实现-Call FPGA implementation of the IP core FFT computation, in the Xilinx implementation of the vertex4sx55FPGA
Simulation-and-FPGA-Implementation-of-DigitalDBPSK
- 文章介绍了系统的硬件电路原理与具体实现方法，其中主要包括载波恢 复电路，PN 码捕获电路和跟踪电路，并针对Xilinx 公司FPGA 的特点，对各电 路的实现进行优化设计，在不影响系统稳定性和精度的前提下，减少硬件资源 消耗，提高硬件利用率。设计利用Verilog 硬件描述语言完成，通过后仿真验证 电路正确性，并给出综合结果。-This paper introduces the system' s hardware circuit principle and the spe
coeff_rom_3_4
- FIR filter basic verilog code for implementation-FIR filter basic verilog code for implementation
fir_liujiao
- 利用verilog语言设计实现8路FIR滤波-Using verilog Language Design and Implementation of 8-channel FIR filter
UART
- 是使用ISE实现UART通信功能，可以提高你的FPGA能力。-Is to use the ISE implementation UART communication can improve the ability of your FPGA.
A-IMPLEMENTATION-OF-TELEMETRY
- Implementation of telemetry link
aes
- 高级加密标准AES的FPGA实现，支持128，256密钥长度格式-Advanced Encryption Standard AES, FPGA implementation to support 128,256 key length format
ProjectreportOFDMTXRX
- OFDM implementation in VHDL/
dds_final
- 使用Verilog HDL语言实现的一个DDS，可以发生0-10Mhz正弦波、方波、三角波，频率步进可调，FM调制、AM调制，调制度可调。DA芯片为8位并行，160MHz-Using the Verilog HDL language implementation of a DDS, can occur 0-10Mhz sine, square, triangle wave, frequency step tunable, FM modulation, AM modulation, adjusta
rsa
- FORFPGA IMPLEMENTATION OF RSA ALGORITHM USING HDL
GPS
- 基于fpga的gps实现。代码完全可用 基于fpga的gps实现。代码完全可用-Fpga implementation based on the gps. Code fully available
FIR
- 实现FIR滤波，利用Verilog语言对其进行了设计 -FIR filter implementation using Verilog language design was carried out