搜索资源列表
Lab1-INTRO
- vcs tutorial lab1，very good
lab1
- xilinx sopc技术实例，请多多指教。一个很小的代码
Lab1_FPGA
- lab1——FPGA这个文件中体统了如何如何使用verilog Hdl以及如何使其在FPGA开发板上实现
lab1
- edk9.1嵌入式开发实验1代码，关于MB何构造一个简单硬件系统-Embedded Development edk9.1 code in Experiment 1, on the MB He constructed a simple hardware system
lab1
- lab1 report, with code -lab1 report, with codelab1 report, with code
lab1
- system generator/simulink 应用开发实例，User Starting
lab1
- VHDL USER GUIDE_ GOOD-GUIDE FOR NEW USER
lab1
- DE2开发板配套LAB1里面源代码，一共六部分。-DE2 development board s source of lab1,which is seperated to 6 parts.
XC4VLX60MB_Lab5_PROM_ISE91
- XCVLXMB the board Xilinx SRAM_BASED FPGA design is the main element Pieces, SRAM_BASED the FPGA, the design began to verify the results, may experience many changes, this time as long as the JTAG s DOWNLOAD CABLE with the IMPACT software is conti
lab1-lab3
- XILINX EDK中三个简单的实例！有PDF详细说明-XILINX EDK in three simple examples! A PDF details
lab1
- 对xilinx 的edk软件的基本操作，对一些基本逻辑操作的控制-xilinx edk
Lab1
- xilinx培训资料，配合相应的PDF文件使用 共20个，先上传一部分，其他的有需要再上传-xilinx training materials, with the corresponding PDF file using a total of 20, first upload a part of, the other the need to re-upload
lab1
- labs in verilog it consists of lab work from design of mux adders from primitives
lab1(mka)
- RGB vga driver for manipulating the colours of a given image buffer. The code has beeen written in vhdl
Lab1
- Lab1 Altera about VHDL
lab1
- 本实验主要设计基本的门电路，包括两输入与门，两输入与非门，两输入或门，两输入 或非门，两输入异或门，两输入同或门。-In this study, the basic design of the main gates, including two input AND gate, two input NAND gate, two input OR gate, the two input NOR gate, the two input XOR gate with two input OR gate
lab1
- xilinx官网edk实验，lab1，用nexys 2 板实验源代码-xilinx edk official website experiments, lab1, with nexys 2 plate test source code
lab1
- chuc cac chu vui ve voi dong tai lieu nay nhe
Computer-Architecture-lab1
- 计算机组成实验作业1，fpga开发板，verilog语言编写-Composition of experimental computer operating 1, fpga development board, verilog language
LAB1-TEXT
- LAB 1 - Basic Verilog