搜索资源列表
rtl
- 用verilog编写的网卡芯片rtl级。前仿后仿都通过了，可以在modelsim上运行察看-verilogrtl After the former imitation through imitation, it can run on the look modelsim
ping_pang
- 这是用AHDL语言编写的一个PCI采集系统的逻辑源码，其中的乒乓设计思路新颖，有兴趣的朋友可以参考一下！编译环境为maxplus2-This is AHDL prepared a PCI Acquisition System logical source, the Table Tennis novel design concept, interested friends can take a look! Build environment for maxplus2
8051IPCORE
- VHDL写成的8051IP核，仔细看能有不少收货-written in VHDL 8051IP nuclear, look very carefully to have a receipt
VHDcf_fft_1024_8
- 1024点８位FFT的VHDL语言实现方式，大家可以参考一下。-1024-point FFT eight VHDL way, we can take a look.
matlab-fft
- FFT的MATLAB的实现方式，自己试过，大家可以参考一下。-FFT MATLAB way to achieve their tried, we could take a look.
fft.c
- C语言实现快速傅立叶变换，大家可以参考一下！-C language Fast Fourier Transform, we can take a look!
yyin
- 这是一个语音程序,通过VHDL编译了.大家可以直接调用.其中还包括了键盘程序有需要可以下来-This a voice procedures, through a VHDL compiler. you can directly call. It also includes a keyboard procedures need to look at it down
DaFilter
- /* This program generates the DApkg.vhd file that is used to define * the DA filter core and gives its parameters and the contents of the * Distributed Arithmetic Look-up-table \"DALUT\" according to the DA algorithm-/ * This program generate
Seg_HLD3Core(400)_(C)
- 这是非常好的vhdl例子，大家看看吧，希望与大家分享更多的好东西-It is a very good vhdl example, we look at it, and we hope to share more good things
Music_HLD3Core(400)_(C)
- 这是非常好的vhdl例子，大家看看吧，希望与大家分享更多的好东西-It is a very good vhdl example, we look at it, and we hope to share more good things
SN7448
- 这是非常好的vhdl例子，大家看看吧，希望与大家分享更多的好东西-It is a very good vhdl example, we look at it, and we hope to share more good things
bin2bcd7
- 这是非常好的vhdl例子，大家看看吧，希望与大家分享更多的好东西-It is a very good vhdl example, we look at it, and we hope to share more good things
16bit-CLA
- 16 bit carry look ahead adder verilog code
cla16
- verilog code 16-bit carry look-ahead adder output [15:0] sum // 相加總和 output carryout // 進位 input [15:0] A_in // 輸入A input [15:0] B_in // 輸入B input carryin // 第一級進位 C0 -verilog code16-bit carry look-ahead adderoutput [15:0] sum// sum of
32bitcarrylookaheadadder
- 32位超前进位加法器的源代码和testbench-32 bit carry look ahead adder and its testbench
CLA
- carry look ahead adder
4_Bit_CLA_4.0.vhd
- 4-Bit Carry Look Ahead adder
adder1
- adder Ripple Carry Adder(RCA) Carry Look-ahead Adder(CLA) Block Ripple Carry Adder(BRCA) Two-Level Carry Look-ahead Adder-Ripple Carry Adder(RCA) Carry Look-ahead Adder(CLA) Block Ripple
carry-look-ahead-adder32
- This implements Carry look ahead adder in verilog
64Bit-Look-Ahead-Adder-Verilog-Code-with-Testbenc
- 64Bit Look Ahead Adder Verilog Code with Testbench