搜索资源列表
mcode
- 一个典型的m序列发生器，生成m序列:1110010-a typical sequence generator m, m Sequence Generation : 1110010
M-150_tm_eng
- M-150II打印机芯开发资料,广泛用于出租车记价器与消防记录仪!
m.rar
- 扩频接收机设计的部分，一个用vhdl语言编写的m序列生成器，,A language with vhdl generator sequence m
fpdpsk
- FSK/PSK信号调制器的VHDL程序，共分为分频器、m序列产生器、跳变检测、2:1数据选择器、正弦波信号产生器和DAC(数、模变换器)6部分-FSK/PSK signal modulator VHDL program is divided into divider, m sequence generator, transition detection, 2:1 data selector, the sine wave signal generator and DAC (number, mode
Matlab-m-sequence-generator
- 介绍m序列和教你如何利用matlab进行编译m序列-Introduction of m-sequences and teach you how to use the matlab compiled m-sequence
M-sequence-generator
- M sequence generator using VHDL-M sequence generator
M
- 小M序列发生器。序列长度为7。方便修改。-Small M sequence generator. Sequence length is 7. Facilitate the change.
m
- 由20位移位寄存器线性反馈产生的m序列的vhdl代码-20-bit shift register linear feedback sequence generated vhdl code m
communications_1
- 用vhdl代码描述的通信系统仿真程序。包括信源（20位m序列），crc编码（采用串行算法），加噪（用22位m序列产生稀疏的1，然后和编码后的数据异或）。-Vhdl code with the simulation program described in the communication system. Including the source (20 m sequence), crc code (using the serial algorithm), noise (with 22 m se
m
- m序列生成文件，带有我自己写的仿真，结果在modelsim6.0f中生成正确。-m sequence generation file, written with my own simulation results generated in the modelsim6.0f correct.
LIP1732CORE_system_mbus_arbiter
- System Verilog M bus arbiter module
m_sequencer
- m序列发生器，长度可以变化，此处使用长度为40 的移位寄存器。反馈函数使用的是：x40+x5+x4+x3+1-m sequence generator, the length can be varied. here the length of the shift register is 40. Feedback function : x40+ x5+ x4+ x3+1
m
- m序列产生器，verilog语言实现,在FPGA上试验过-m code maker
m_m
- 这是我写的一篇论文中关于m序列及M序列的源代码及各个模块所编写的testbench。各个模块编写正确，有关爱好者可以在之上进行扩展。-This is a paper I wrote on the m series and M series, and each module source code written testbench. Preparation of each module correctly, the lovers can be extended over.
Verilog----m
- verilog 编写的m 序列，可以直接使用。-verilog written m-sequence can be used directly.
FPGA-M-sequence-generator
- FPGA VHDL 语言M序列发生器，可以帮助各位需要的朋友探讨研究-FPGA VHDL language M-sequence generator, can you help a friend in need of research
m-xulie
- 频率可步进M序列发生器 从10K 到100K ,步进为10K VERILOG编写-M-sequence generator frequency step from 10K to 100K, the preparation step for the 10K VERILOG
M-sequence
- M序列具有伪随机特性，代码包含了M序列的生成和检测，可用于帧同步系统。-M-sequence has a pseudo-random properties, including the M-sequence code generation and detection, can be used for frame synchronization system.
m-sequence_gen
- m序列生成verilog代码，经过仿真测试，绝对可用，带仿真说明-M sequence generated Verilog code, after the simulation test, absolutely available, with the simulation
spec.tar
- M.2 testing specification