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baijinzhi
- 利用扫描加记数程序实现百进制,适合VHDL的初学者使用.-increase in the use of scanning program in mind several hundred 229 and is suitable for beginners to use VHDL.
s3esk_startup
- 利用kcpsm3控制lcd显示 平台：ise 10.1， picoblaze， Spartan3e 开发板 说明：综合按键和lcd、led的功能，思想简单，需要新技术，适合想在fpga方面深造的人。-using kcpsm3 for lcd display platform: ise 10.1， picoblaze， Spartan-3E FPGA Starter Kit Board comment: involve lcd/led/switch, simple mind bu
taxi_price
- 出租车记价器，使用vhdl语言编写的源码及其仿真。-Taxi price of devices in mind, use the source code written in vhdl and simulation.
qiangdaqi-EDA
- 智能抢答器的EDA实现： 1． 四人参赛每人一个按钮，主持人一个，按下就开始； 2． 每人一个发光二极管，抢中者灯亮； 3． 有人抢答时，喇叭响两秒； 4． 抢答时限10秒，从有人抢答开始记时，10秒内不回答问题时喇叭发出两秒声响 -Smart Responder of EDA to achieve: 1. Four entries per person of a button, a moderator, click on Start 2. Each a light-emi
HowToStartFpgaDesign
- 怎样开始fpga设计，文中是我看了一本书的笔记，用思维导图软件记录的，感觉这种方法不错，希望有更多的人采用，增加学习效率。-How to start fpga design, the paper is a book I read the notes, use mind mapping software, records, and feel good this way, I hope more people use, to increase learning efficiency.
9.59
- 实现9分59秒的记时功能 当输入1Hz的脉冲时，且START置1时，能正常记时，当将RESET置1时，可以实现复位功能 当将STOP置1时，可以停止记时，记时的能记到9分59秒-9 minutes and 59 seconds to achieve when the mind functions when the input pulse 1Hz, and START is set to 1, to normal mind, and when the RESET is set to 1 w
synth_fft
- fftprocessing can complete 256 pointsFFT.-Hardware Descr iption Language(HDL)is an advanced electronic designmethod．After HDL was put into use，it has draw great attention and gained popularity．The design used Verilog HDL and Schematic for entry tools
qiangdaqi
- 基于VHDL与FPGA的四路抢答器的设计与仿真。主要模块：抢答、竞争冒险、抢答倒计时、加分减分、超时蜂鸣、按键消抖、答题记时等模块-VHDL and FPGA-based four-way Responder Design and Simulation. Main modules: Responder, competition and adventure, answer in the countdown, plus minus points, overtime buzzer, key debou
A-Simplified-VHDL-UART
- In embedded systems, the processor that we choose for our design may not come with built-in peripherals. Therefore, designers will have to implement these devices in hardware keeping in mind that they will need to interface to the processor. In this
FPGA-zhengqie
- 可以考虑利用FPGA来构成系统检测获取偏振图像的Stokes矢量，而 由Stokes矢量来计算偏振角利用FPGA实现就比较复杂，往往又利用软件来实现，这 与最初利用FPGA硬件实现偏振图像的Stokes矢量计算达到实时性要求的初衷不符， 因此有必要设计出一种利用FPGA来硬件实现actan函数的计算的方法。 -Can be considered to constitute a system test using FPGA to obtain polarization images
miaobiao
- 秒表计时功能,可以从零记到九十九，可以暂停，可以清零。-Stopwatch functions, from zero in mind to 99, you can pause, can be cleared.
RISC-CPU
- 精简指令集 CPU 通过仿真验证正确 (使用之前务必看readme文件，和结构图!) 1. 此cpu是夏宇闻 verilog数字系统设计教程中最后一章的例程。 2. 学习时务必先搞明白框图原理，和数据流动！！！ 3. 牢记主状态机中一条指令周期中传输的16bit=3bit指令+13bit地址。 4. 理解数据总线，和地址总线。区分数据和地址。 5. 仔细调试，因为书中有很多小错误。 程序经过quartusii编译通过，另外经过modelsim仿真正确。-RISC
XU-LIE-JIAN-CE-QI
- 用状态机实现序列检测器的源代码，用maxplus软件运行，管脚已配置完成，芯片为EP1K30TC144-3-State of mind achieved with a sequence detector source code, run the software with maxplus Pin has been configured, the chip is EP1K30TC144-3