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trunk-hdlc.rar
- 高级链路层协议的实现，vhdl，fpga,- 8 bit parallel backend interface - use external RX and TX clocks - Start and end of frame pattern generation - Start and end of frame pattern checking - Idle pattern generation and detection (all ones) - Idle pattern
alu_wide2
- Generating a wider ALU from two small ones
vhdl_pgms
- Program for Counter, mealy machine, moore machine, ones counter, seven segment with zero blanking and shift register in VHDL.
parity_generator
- parity generator Parity bits are extra signals which are added to a data word to enable error checking. There are two types of Parity - even and odd. An even parity generator will produce a logic 1 at its output if the data word contains an odd num
Estimating19609112312005
- Simple exercise that calculate the Taylor expansion of the exponential function. Input variables: degree N vector of evaluation points, x At each step plots the Taylor polynomial and compare with the real function function y=
ones_counter
- Ones counter for Verilog, basic project for Altera FPGA
FPGA_ARINC_429_design
- 机载数据总线ARINC 429在当代的运输机和相当数量的民用客机中有着广泛的应用。目前国内的专用ARINC 429信号处理芯片一般路数有限,要实现多通道的信息处理,就需要多块类似的芯片,从而体积就会变的比较庞大,非常不灵活。,因此利用FPGA和DSP相结合,设计和研制的ARINC 429总线信号处理板,成为目前飞机机载总线接口研究的重点,具有非常重要的现实意义和应用前景。 -The airborne data bus, ARINC 429 has a wide range of modern
Four-Consecutive-Ones-Detector
- its a counter of four ones consecutive
eatfish
- vhdl语言，可以实现大鱼吃小鱼功能的时钟仿真仿真，经过测试可用-vhdl language, can achieve ones devour function clock simulation simulation, tested available
led
- LED译码电路设计，实现LED显示以及扫描电路。该程序采用共阴极。主要的两点为能够自动适应扫描电路的路数.-LED decoder circuit design, implementation, LED display, and the scanning circuit. The program uses a common cathode. The main points to be able to automatically adapt to the large ones scanning c
工作簿1
- 主要关于合肥工业大学计算机方面的知识，有数据结构，计算机组成原理，java，面向对象，(Just hole teacher talk, so that six new development of the party, you find a time, with the volunteer book, together to find the blue Secretary talk, @ Wang Kuo, you're responsible for this thing, a common