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convolution_encoder_VHDL
- 卷积码编译码,由SERVICE、PSDU、TAIL和PAD域组成的DATA域应进行卷积编码，码率应根据所需的传输速率从R=1/2,2/3,3/4中选择-for 802.11a simulation WLAN FEC convolution_encoder g0=133 g1=171 Rate 0:1/2 1:2/3 2:3/4 for 802.11a simulation
tPad_Picture_Viewer
- tPad DE2-115/70可用的图片浏览设计程序，原装程序，可下载到带触摸板的DE2开发板上调试，代码可修改-tPad DE2-115/70 picture browsing design program available, the original program, with a touch pad can be downloaded to the DE2 board debugging, code can be modified
DFNL
- On-chip synchronization is achieved by connecting the CLKFB input to a point on the global clock network driven by a BUFG, a global clock buffer. The BUFG connected to the CLKFB input of the DCM must be sourced from either the CLK0 or CLK2X out
44key-pad
- 用verilog hdl语言实现4*4键盘扫描的小程序-With the verilog hdl language 4* 4 keyboard scan applet
Manual-elevator-controller
- 电梯控制器，是集读卡、密码键盘于一体的智能控制设备，通过该设备可以有效管理电梯乘坐人员的乱乘行为。-Elevator controller, is a card reader, PIN pad in one of the intelligent control device, the device can be effectively managed through the elevator ride by chaotic behavior of staff.
NEW_File
- A-C8V4开发板SD卡读写测试:通过此程序文件可以对A_C8V4开发板进行SD卡读写测试-A-C8V4 pad s SD test about read and write
PADTOKEY
- 将开发板上的按键转换成按键码，对键盘进行识别。-scan key pad
DE2_ControlPanel_V2.0.1
- de2 Cyclone® II 2C35 FPGA 最新版 控制面板-de2 Cyclone® II 2C35 FPGA control pad
I2Csalve.v
- Modified I2C salve design 1. Asynchronous design: ASIC or FPGA design option 2. 8 bits CSR RW interface: 0~15, address and control 3. PAD not included 4. Altera CPLD verified