搜索资源列表
一些译码器源代码
- 内有LED译码器，汉明纠错译码器，地址译码器，最高优先译码器，双2－4译码器等VHDL的源代码-decoder, Hamming error correction decoder, address decoder, the highest priority decoder, dual 2-4 decoder such as VHDL source code
8899
- 最高优先级编码器，是特别好的东西，好不容易才弄到的．-highest priority encoder, is especially good things, the result of the hard-won.
VHDL_Development_Board_Sources
- 这是我最近买的一套CPLD开发板VHDL源程序并附上开发板的原理图,希望对你是一个很好的帮助!其中内容为:8位优先编码器,乘法器,多路选择器,二进制转BCD码,加法器,减法器,简单状态机,四位比较器,7段数码管,i2c总线,lcd液晶显示,拨码开关,串口,蜂鸣器,矩阵键盘,跑马灯,交通灯,数字时钟.-which I have recently bought a CPLD Development Board VHDL source code accompanied the development
Verilog_Development_Board_Sources
- 朋友，我是Jawen.看到先前上载的一套CPLD开发板的VHDL源码挺受欢迎的，现在就将她的Verilog源码也一并贡献给大家：8位优先编码器,乘法器,多路选择器,二进制转BCD码,加法器,减法器,简单状态机,四位比较器,7段数码管,i2c总线,lcd液晶显示,拨码开关,串口,蜂鸣器,矩阵键盘,跑马灯,交通灯,数字时钟-friends, I Jawen. previously seen on the set of CPLD Development Board VHDL source code q
verlog_basic
- 用verlog语言编的一些基础实验,适合于FPGA/CPLD的初学者。内容包括8位优先编码器，乘法器，除法器，多路选择器，二进制转BCD码，加法器，减法器等等。-verlog used some language addendum to the basic experiment, which is suitable for FPGA / CPLD beginners. Including eight priority encoder, multipliers, dividers, multi-p
用assign 语句描述的三态门
- 用assign 语句描述的三态门，三态双向驱动器，3-8 译码器，8-3 优先编码器等等,With the assign statement describing the three-state gate, three-state bi-directional drive, 3-8 decoder ,8-3 priority encoder, etc.
arbiter.rar
- 一个用verilog编写的总线仲裁程序。多个设备共享总线，不同设备的优先级是变化的，保证每个设备都有公平的使用总线的机会。,Verilog prepared a bus with arbitration proceedings. Multiple devices share the bus, the priority of different devices is changing to ensure that each device will have a fair opportunity t
elevator.rar
- verilog语言写的一个四层电梯程序，有优先级的判断。,verilog language of a four-story elevator procedures to determine priority.
encode
- 8位优先编码器。 8位优先编码器。-8-bit priority encoder. 8-bit priority encoder. 8-bit priority encoder.
cnt8bc
- 8位加减带异步复位计数器，使用双向输入管脚- Design an 8-bit up and down synchronous counter in VHDL with the following features: The same ports are used for signals to be inputted and outputted. The ports are bi-directionally buffered. The counter is with an asynch
vhdl
- 最高优先级编码器和直流电机控制器,供初学者学习使用，方便快捷，有很强的参考价值-The highest priority encoder and DC motor controller, for beginners learning to use, convenient and has a strong reference value
priority
- Priority encoder in VHDL.
penc81
- 8:1 priority encoder.. Test Bench included-8:1 priority encoder.. Test Bench included..
PRIORITY_ENCODER
- A priority encoder is a circuit or algorithm that compresses multiple binary inputs into a smaller number of outputs. The output of a priority encoder is the binary representation of the ordinal number starting from zero of the most significant input
Priority-encoder
- 在Quartus II中用VHDL语言编写的优先级编码器程序-In the Quartus II VHDL language using the priority encoder program
Eight-priority-encoder
- 八位的优先编码器 具有优先编码的功能 程序简单易懂-Eight priority encoder
Interrupt-priority-levels
- 用流水灯或数码管显示实现8051芯片的中断优先级功能。-Lamp or water pipe with a digital display of 8051 s interrupt priority feature.
Priority-encoder
- priority encoders(3:8)(2:4)
Priority-encoder
- 用VHDL语言编程来实现优先编码器的功能。-VHDL language programming to achieve priority encoder function.
SV-Priority
- system Verilog priority