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DDS小数分频
- 文件列表(点击判断是否您需要的文件，如果是垃圾请在下面评价投诉): DDS小数分频 ...........\Block1.vhd.bak ...........\db ...........\..\add_sub_9mh.tdf ...........\..\DDS.asm.qmsg ...........\..\DDS.asm_labs.ddb ...........\..\DDS.cbx.xml ...........\..\DDS.cmp.
LogicLock
- logiclock功能演示 用vhdl语言编写 quartus环境实现-logiclock functional demo vhdl language environment for realization of quartus
or1200_wb_ram_gpio_pll
- Quartus ii项目，硬件平台为SOPC2000，能实现LED的各种显示控制及按键输入。包括硬件实现的Verilog及软件实现的C实现。SOPC系统的设计在Windows的quaruts ii 8.0上实现，软件部分在Ubuntu上实现。-Quartus ii project, the hardware platform for SOPC2000, to achieve a variety of LED display control and key input. Including Ver
zhengzhoueda1
- 用vhdl语言的fsk调制，所有文件都都齐全，只需要打开zhengzhoueda1.qpf就行了-Fsk modulation using vhdl language, all files are complete, just open zhengzhoueda1.qpf on the line
traffic.qpf
- 设计一个主干道和支干道十字路口的交通灯控制电路，主干道绿灯亮、支干道红灯亮，并且主干道绿灯亮的时间不得少于60秒。-Design a main road and branch roads intersection traffic lights control circuit, the main road the green light, branch roads red light, green light and the main road is not less than 60 second
dianzibiao
- verilog语言编写的多功能电子表程序-verilog language, multi-function electronic spreadsheet programs
timing_controller
- 本程序为船舶导航雷达时序控制模块的整个系统，包含QPF工程。-The program for the entire ship navigation radar system timing control module contains the QPF project.
antenna_position
- 本程序为船舶导航雷达天线方位部分的verilog程序，包含QPF工程。-This procedure for the marine navigation radar antenna part of the Verilog program, including QPF works.