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misunderstanding_in_FPGA
- FPGA设计中的误解。包括成本节约，低功耗设计，系统效率，信号完整性，可靠性设计-FPGA design misunderstandings. Including cost-saving, low-power design, system efficiency, signal integrity, reliability design
yuyincaiji
- 语音采集与回放系统源代码：1.为了使读音数据存储的时间更长，速度更快，选用了256K*16Bit的SRAM；2.为了减少单片机的控制复杂度，使用了FPGA来控制SRAM的读写操作，节约了不少单片机的I/O资源；3.为了以后的高速数据存储，本设计中加入了fifo,其位宽及深度可在程序中自由设置，方便灵活。-Speech acquisition and playback system source code: 1. In order to make pronunciation longer data
RECURSIVEALGORITHMFOREFFICIENTMAPDECODING
- Early termination enables powering down parts of the soft-input soft-output (SISO) equalizer and decoder thereby saving power.
10512210247008
- 该数字式相位测量仪以单片机 (89c52) 为核心 , 通过高速计数器 CD4040 为计数器计算脉冲个数从 , 而达到计算相位的要求 , 通过 8279 驱动数码管显示正弦波的频率，不采用一般的模拟的振动器产生 , 而是采用单片机产生 , 从而实现了产生到显示的数字化 . 具有产生的频率精确 , 稳定的特点 . 相移部分采用一般的 RC 移相电路 , 节省了成本。-The digital phase-measuring instrument in order to microcontrolle
Cordic-VHDL
- Cordic算法的VHDL实现,可作为函数调用的代码，节省自己的设计时间-Cordic algorithm VHDL implementation of the code as function calls, saving their own design time
can
- can bus is used to transfer data faster and also power saving-can bus is used to transfer data faster and also power saving............
multplier-VerilogHDL
- 利用VerilogHDL语言编写的各种各样的乘法器，比如并列乘法器，省时乘法器等-VerilogHDL language using a variety of multipliers, such as parallel multipliers, multiplier and other time-saving
jiaotongdengxitongsheji
- 交通灯系统设计，能更好的优化交通灯的系统，节省资源，效益最大化-Traffic light system design, to better optimize the traffic light system, saving resources, to maximize efficiency
time
- 用单片机及位LED数码管显示时分秒，以及24时的计时方式运行。能够整点提醒（短蜂鸣，次数代表整点时间），使用按键开关可实现时，分调整，秒表/时钟功能转换，省电（关闭显示）及定时设定提醒（蜂鸣器）等功能-With the microcontroller and LED digital tube display minutes and seconds, and 24 hours of run time. Reminded that the whole (short beep, the number
jiandan28
- 基于VHDL的CPLD频率计，考虑节省资源的设计方案-Based on VHDL CPLD frequency meter, consider a resource-saving design
msp430x41x
- 低电源电压范围为1.8 V至3.6 V 超低功耗： - 主动模式：280μA，在1 MHz，2.2伏 - 待机模式：1.1μA - 关闭模式（RAM保持）：0.1μA 五省电模式 欠待机模式唤醒 超过6微秒 16位RISC架构， 125 ns指令周期时间 12位A/ D转换器具有内部 参考，采样和保持，并 AutoScan功能 16位Timer_B随着三† 或七‡ 捕捉/比较随着阴影寄存器 具有三个16位定时
A7105-Datasheet-v1.1
- 无线A7105说明书 0.0 Initial issue. 0.1 Modified specification and add section for TX power setting 0.2 Add top marking info., reflow profile, Carry tape & reel dimensi 0.3 Modify descr iption of state machine and FIFO mode Rename IRQS1/
CICzhengli
- 整合本站所有CIC滤波器能用的下载，并给出最好的选择，节省您的时间，花一次费用享受多次代码下载-Integration site CIC filter can download and gives the best choice, saving you the time to spend a one-time cost to enjoy several Codes
lut
- 可参数化配置的CAM模块，仿照xilinx IP core设计而成，使用SRL16E基本单元实现，节省空间-Can be parameterized configurable CAM module, modeled xilinx IP core designed, implemented using the basic unit SRL16E, space-saving
t1_bin2bcd
- 二进制转BCD的verilog程序，实现二进制数到BCD的转换，该程序具有节约FPGA的内部逻辑资源等特点- Binary to BCD s verilog procedures to achieve binary number to BCD conversion, the program has an inter
rs_decoder_31_19_6_latest.tar
- 31.19解码器- RS code is the BCH code of multi-systerm, after a long time of development, the theory and technology of RS code has been rather mature that it can rectify burst error and random error at the same time, especially burst error. It is widel
fir
- 利用系数奇对称的性，节约一半乘法器资源，实现平行FIR滤波器的功能。-The function of parallel FIR filter is realized by using oddly symmetric coefficients and saving half of the multiplier resources.
drvgh
- Weighted acceleration, Is a two hidden layer back propagation neural network, Implemented with SDRAM run nios, while saving camera data SRAM.
sh478
- GPS and INS navigation program, Implemented with SDRAM run nios, while saving camera data SRAM, Calculation crosshairs diffraction image at different distances.