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mc8051V1.4
- 8051硬核源码（VHDL），具有全部VHDL代码、测试环境以及说明文档、综合脚本等完整的开发、验证环境，源代码通过ASIC投片，并得到不断完善-8,051 hard-core source code (VHDL), with all VHDL code, testing and documentation, environment, Comprehensive integrity of the scr ipt, such as development, certification, the s
7状态机设计
- 这是“状态机设计（讲稿）”，希望对正在学VHDL的同学有帮助，谢谢！-This is the "state machine design (the scr ipt)", and I hope to learn VHDL is there to help the students, thank you!
VHDL设计进阶
- 这是“VHDL设计”讲稿，希望对初学者有用，-"VHDL design" scr ipt, useful for beginners, thank you! !
modelsim.rar
- 学习modelsim脚本仿真的绝佳范例,很强大啊,Modelsim simulation study and an excellent example of a scr ipt
FPGAdesignrule
- 一个很好的讲稿，希望大家多提意见，呵呵。-A very good scr ipt, hope that we do so, huh, huh.
gen_tb
- 用于verlilog自动产生testbench的脚本 用法：gen_tb <yourfilename>-Testbench for verlilog automatically generated scr ipt usage: gen_tb <yourfilename>
2008.09-scripts_only
- synopsys icc 使用参考脚本-reference scr ipt of synopsys icc
presentation_pfe_v3.6.ppt
- Jtag communication design with VHDL scr ipt
freq
- a verilog hdl code that contains scr ipt for dividing frequencies in ACEX1K Altera FPGA Board.
asic_scrip_taiwan
- 台湾中山大学ASIC实验室综合脚本教程,对学习，编写ASIC综合脚本有很大帮助哈。-synthesize scr ipt guide for ASIC
verilog
- 北航夏宇闻verilog讲稿ppt语法入门-Wen Yu Xia Beihang verilog scr ipt syntax entry ppt
64pointFFTR2MDC
- 该工程实现了一个64点DIF FFT，verilog编写，采用R2MDC结构，通过Modelsim功能仿真，压缩包里有rtl代码，dc脚本，输出报告。-The project implements a 64-point DIF FFT, verilog compiled by R2MDC structure, through the Modelsim functional simulation, compression bag with rtl code, dc scr ipt, the out
dsp_ohp
- Digital signal processing overhead slides in post scr ipt format
Modelsim--script-usage
- modelsim是Mentor graphics公司推出的HDL代码仿真工具，也是业界最流行的HDL仿真工具之一。支持图形界面操作和脚本操作。常见的图形界面操作相对直观，但是由于重复性操作几率高、处理效率低、工程的非保存性，对于大规模的代码仿真不推荐使用；脚本操作完全可以克服以上的缺点，把常见的命令，比如库文件和RTL加载、仿真、波形显示等命令编辑成.do脚本文件，只需要让Modelsim运行.do文件即可以完成仿真，智能化程度高。本文重点介绍Modelsim常见命令的使用，以及如何使用.do
6soft_247MHz_channel
- lte上行信道解交织解复用: RTL: ack_addr_gen.vhd ack地址产生 data_addr_gen.vhd 数据地址产生 de_interl_mux_con_ctrl.vhd 控制单元 de_interl_mux_con_top.vhd 顶层 de_interl_mux_con_tt.vhd 测试平台 de_mux_ram.vhd ram deinterl_pack.vhd 变量定义 delay.vhd 延迟 delayb.vhd 延迟
verilogppt
- 北航夏宇闻的Verilog的PPT讲稿，挺经典的，适合初学者学习-Northern Xia Yu Wen' s Verilog the PPT scr ipt, very classic, suitable for beginners to learn
script
- fpga设计中用vhdl写的屏幕程序，在使用康芯等公司的最小系统芯片中有很好的效果。-fpga design using vhdl to write the screen program, such as the use of health-core chips in the company' s smallest system, have a good effect.
Perl_for_CRC
- Cyclic Redundancy Check (CRC) is an error-checking code that is widely used in data communication systems and other serial data transmission systems. CRC is based on polynomial manipulations using modulo arithmetic. Some of the common Cyclic Redu
SVA-script
- 一个自己总结的systemverilog assertion读书笔记，基本上systemverilog assertion的语法比较全。简单易懂。适合SVA入门。-systemverilog assertion scr ipt
windows-script
- 在window平台，采用脚本TCL来编译fpga的经典例子。具体的写法，见工程中的ise_flow.bat文件。如果在工作站来处理更块-In the window platform, using classic example TCL scr ipt to compile the fpga. Specific wording, see the project ise_flow.bat file. If the workstation to handle more blocks