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generic_fifos
- 用HDL语言编写的通用fifo源码，通过对fifo的宽度和深度进行配置，可以产生我们所需要的fifo，还包括fifo的测试程序和仿真Makefile脚本-with HDL prepared by the General fifo source, fifo of the breadth and depth configuration, can produce what we need fifo. also included fifo testing procedures and simulatio
crc_gen.pl
- CRC verilog 生成脚本，可自己设定CRC 参数-CRC verilog generate scr ipts, you can set their own parameters CRC
asic_study
- 压缩包中是ASCI学习资料，包括一个台湾中山大学ASIC实验室综合脚本教程，一本springer出版的交大家用system verilog做验证的书，还有一个xilinx论证的XAPP726 - 无线基站基带处理应用中的FPGA的理由。对大家做通信后端设计很有帮助。-ASCI is compressed package learning materials, including a laboratory in Taiwan Sun Yat-ASIC synthesis scr ipts tuto
robust_fir_latest.tar
- RobustVerilog generic FIR filter In order to create the Verilog design use the run.sh scr ipt in the run directory (notice that the run scr ipts calls the robust binary (RobustVerilog parser)). The filter can be built according to 3 differe
6_Sets_of_8051_VHDL_Verilog
- it has 6 packages of 8051 sources,including source code(VHDL and Verilog),dc scr ipts, pdfs, netlists etc. and a MIPS IP package
ex_DDS
- 基于Verilog语言实现DDS（数字频率合成器）的设计，有完整的工程设计代码和仿真脚本(Verilog language based on DDS (digital frequency synthesizer) design, there is a complete engineering design code and simulation scr ipts)
scripts
- 低通滤波器的实现，通过不同的切割方式实现后，生成的vivado文件资源的使用情况不同，对其进行分析(The implementation of the low pass filter, after the implementation of different cutting methods, the use of the generated vivado file resources is different, to analyze it.)