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cf_vhdl
- CF VHDL The CF+ design was designed using the timing diagrams of the Compact Flash specification rev. 1.4, Analog Devices ADSP-218xN DSP Microcomputer specification, and the Intel StrataFlash Memory 28F320J3 specification.
wisbone_2_ahb.tar
- ---- ---- ---- WISHBONE Wishbone_BFM IP Core ---- ---- ---- ---- This file is part of the Wishbone_BFM project ---- ---- http://www.opencores.org/cores/Wishbone_BFM/ ---- ---- ---- ---- Descr iption ---- ---- Implementation of Wishbone_
wb_rtc
- // -*- Mode: Verilog -*- // Filename : wb_master.v // Descr iption : Wishbone Master Behavorial // Author : Winefred Washington // Created On : 2002 12 24 // Last Modified By: . // Last Modified On: . // Update Count : 0 // Status : U
c8051
- USB v1.1 RTL and design specification
Coding-style-and-guidelines-of-HDL
- 该资料对数字设计的编码风格、编码规范给出了详细介绍，并简介了VHDL、verilog的编码要点。-The information on the coding style of digital design, coding specification gives a detailed descr iption and profile of VHDL, verilog coding points.
a_vhdl_8253_timer_latest.tar
- 一个apb总线控制8253的verilog源代码，符合标准的amba 2.0的总线规范-A apb bus control 8253 of the verilog source code, amba 2.0 standard bus specification
The-Specification-of-SDC
- 综合约束文件SDC的写法说明 synopsys 出品-Using the Synopsys Design Constraints Format Application Note
pcirw
- quartusII环境下实现FPGA与PCI9054通信。根据PCI9054规范控制lhold、lholda、ads、blast、lbe、lwr等握手信号的时序，可完成上位机通过PCI总线读写FPGA本地地址空间的功能- Communication between FPGA and PCI9054 in QuartusII IDE.Implementation for the timing of handshake signals such as lhold, lholda, ads,bla
XilinxisdisclosingthisSpecification
- Xilinx is disclosing this Specification ? 第 1 章“EMIF 概述”，概述 Texas Instruments EMIF。 ? 第 2 章“Virtex-II 系列或 Spartan-3 FPGA 到 EMIF 的设计”描述将 TI TMSC6000 EMIF 连接到 Virtex?-II 系列或 Spartan?-3 FPGA 的实现。 ? 第 3 章“Virtex-4 FPGA 到 EMIF 的设计” 描述将 TI TMS320C6
FSCQ1565RP
- FSCQ1565RP J TAG驱动算法是MCU 以J TAG模式配置FPGA 的关 键。算法调用SVF 配置文件,解释其中的语法规范,生成严 格的TAP 总线时序,驱动MCU 的通用I/ O 管脚来完成对 FPGA 的配置。其中TAP 时序是算法设计和实现调试的一 个主要方面,时序关系[ 2 ]如图3 所示。-FSCQ1565RPJ TAG-driven algorithm is MCU to configure the FPGA model J TAG key. Algo
dbg_interface
- USB v1.1 RTL and design specification
VHDLcodingStyle
- VHDL设计编码规范 VHDL设计编码规范-VHDL Design Coding Design Coding VHDL specification norms
IPG
- A project Game designed on a DE270 board. It explains all the project and the specification of the used components.
cordic_latest.tar
- Cordic Core Specification
VHDLcoding
- 本文件时VHDL的各种编写规范，有助于开发者在平时养成好的编码习惯-This document, the various write VHDL specification, helps developers to develop good coding habits in peacetime
vhdl-tutorial
- VHDL Tutorial, it describes the modeling language VHDL. VHDL includes facilities for describing logical structure and function of digital systems at a number of levels of abstraction, from system level down to the gate level. It is intended, am
VHDL_Style_Guide
- A style guide for VHDL, the popular hardware descr iptive language for the design/specification of ASICs, FPGAs and CPLDs ICs.-A style guide for VHDL, the popular hardware descr iptive language for the design/specification of ASICs, FPGAs and CPLDs I
AMBA-Specification-Rev-2.0
- AMBA2.0总线协议详细介绍，共230叶英文资料-AMBA2.0 bus protocol details, a total of 230 leaves information in English
sd-2.0-Specification
- Sd Card System 2.0 Specifiction.真实完整版。独此一家。-Sd Card System 2.0 Specifiction. A true and complete version. Alone this one.
verilog-code-style-specification
- 企业用verilog代码风格规范 本规范规定了IC设计项目开发过程中VerilogHDL源代码的编写总则、要求及模板文件。-Enterprises with verilog code style guide for the preparation of this specification General IC design project development process VerilogHDL source code, requirements and template files.