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crack-81
- 最新QuartusII8.1的补丁，安装它的破解器，可以获得长期使用权-QuartusII8.1 the latest patch, install it to break, and access to long-term use rights
FPGA_PWM
- 用Verilog语言编写的FPGA控制PWM的程序.利用码盘脉冲进行调速,进行过简单试验,可用.没有经过长期验证.做简单修改即可应用!-Using Verilog languages FPGA control PWM procedures. Using pulse code disk for governor, conducted a simple test that can be used. Not after a long-term verification. To do a simple
RISC-CPU
- 用FPGA实现一个简易的CPU，采用精简指令集结构，每一条指令有16bit，高三位为指令操作数，后13位为地址，该CPU能实现8种指令操作，分别有HLT（空一个中期）ADD（相加操作）SKZ（为零跳过）AND（相与操作）XOR（异或操作）LDA（读数据）STO（写数据）JMP（无条件跳转指令）。cpu包括8个部件，分别为时钟发生器、指令寄存器、累加器、算术逻辑单元、数据控制器、状态控制器、程序计数器、地址多路器，各个部件之间的相互操作关系由状态控制器来控制，程序指令存放在初始rom中，本例程存放
polynom
- The polynomial solutions of the Hermite differential equation, with n a non-negative integer, are usually normed so that the highest degree term is 2z and called the Hermite polynomials H z. The Hermite polynomials may be defined explicitly by
FPGAFFTEnglish
- 基于FPGA的快速傅里叶变换，中期答辩，的英文资料及翻译。-FPGA-based fast Fourier transform, the medium-term defense, information and translation in English.
99341857matlab
- FFT algorithms FFT, IFFT, power spectrum calculation, including the Hamming window, Hanning window, triangle window, Blackman window, 4 term Blackman-Harris window of several of the power spectrum window function computing power.
SEG
- 7段译码器 吉林大学短学期CPLD实习程序 通过四位拨码开关进行编码，让硬件电路将编码转换成对应的七段码，并将七段码送至数码管进行显示，其中该电路能够输出0到F的16个字符-7 decoder CPLD Jilin University internship program through short-term four DIP switch coded, so that hardware will be encoded into the corresponding seven-segmen
count
- 吉大短学期CPLD实习程序 可逆10 进制计数器，用1 位拨码开关进行加减控制：输入为0 时进行加计数，当输入为1 时进行减计数；用1 位拨码开关进行同步清零控制：输入为0 时清零，输入为1时正常计数。计数结果用数码管显示-Chittagong short term internship program CPLD reversible binary counter 10, with an addition and subtraction DIP switch control: when th
key
- 吉大短学期CPLD实习程序 利用状态机合理的完成了按键去抖的工作，利用EP1C240C8搭建起来的硬件电路能够按照设计者的思路正常工作按照需要的完成了去抖的任务-Chittagong short term internship program CPLD reasonable use of state machine to complete the work of the keys to the shaking, the use of hardware circuits EP1C240C8 b
qiangdaqi
- 吉大短学期CPLD实习程序 设计一个 4 路抢答器，当按下抢答键开始抢答，设置 4 个按键作为 4 路抢答开关，4 个LED 作为抢答显示，一旦抢答成功，蜂鸣器发声，与抢答开关对应的 LED 亮 -Chittagong short term internship program CPLD design a 4-way Responder, Responder to start when you press the answer in, set the four keys as the a
LEDdianzhenxianshi
- 吉大短学期CPLD实习程序 能够完成汉字的循环显示，显示的速度能够通过时钟信号加以控制。 在16×16 LED 点阵上显示汉字-Chittagong short term internship program CPLD to complete the cycle of Chinese characters display, the display speed can be controlled by the clock signal. In the 16 × 16 LED dot mat
trafficlightsa
- 东南大学 短学期数字系统设计中的 交通灯设计 通过状态机实现-Southeast University in the short-term digital system design through the traffic light state machine design
module-Temperature
- DS18B20引脚功能 GND地，DQ数据总线，VDD电源电压 18B20共有三种形式的存储器资源，它们分别是： ROM 只读存储器，用于存放DS18B20ID编码，其前八位是单线系列编码，后面48位是芯片唯一的序列号，最后8位是以上56位的CRC码。DS18B20共64位ROM RAM 数据暂存器，数据掉电后丢失，共9个字节，每个字节8位，第1、2个字节是温度转换后的数据值信息，EEPROM 非易失性记忆体，用于存放长期需要保存的数据，上下限温度报警值和校验数据
term-project
- this project is related with Goal of this system is applying some microprocessor knowledge with use C code on the hardware design. This project is calculating the body mass index value of a person on LCD screen and printing the BMI value. Program nee
-Elliptic
- We present elliptic curve cryptography (ECC) coprocessor, which is dual-field processor with projective coordinator. We have implemented architecture for scalar multiplication, which is key operation in elliptic curve cryptography. Our coproc
Process_Algebra_www.softarchive.net
- Research towards meeting the higher demands for higher data rates was the main reason for the birth of an evolution technology towards the 4th generation mobile communication systems. This evolution to the current 3rd generation UMTS systems
altera-FPGA-Selection-Guide
- altera FPGA 选型指南，有助于在项目前中期根据需要进行响应选型-altera FPGA Selection Guide to help in the project before the mid-term response selection needed
Filter
- 该代码主要实现环路滤波器矩阵的设计，环路滤波器的功能主要是在鉴相器的输出端衰减高频误差分量，以提高抗干扰性能；在环路跳出锁定状态时，提高环路以短期存储，并迅速恢复信号。-The code mainly realizes the design of loop filter matrix, Loop filter function is mainly in the output of the phase discriminator attenuation of high frequency erro
Verilog2
- 在这次程序中只在ROM中存储了一些随机的数，因此显示出来是一些小方格，如果ROM做的更大，完全可以存储一幅图像，显示在LCD中。 不过由于由于用ROM做为显存，每次只能显示一幅静态的图像，而且没有加入字符库，不能显示字符，在下次的文章中，我将使用双口RAM，加上Nios II处理器，这样可以方便的显示各种字符。-My study term ，wish you like