SPI总线接口的verilog源码，包含仿真模块modelsim 和 quartus 工程。本人测试通过。-SPI bus interface in verilog source code, including the simulation module modelsim and quartus project. I test.

AD DA芯片测试程序 (开发环境keilC51+Quartus7.2)-AD DA Chip test program (Developmentenvironment： keilC51+Quartus7.2)

假定系统时钟为50MHz，试设计一个电子秒表电路，使其按0.01s 的步长进行计时。该电子秒表具有异步清零和启动/停止计数功能，最大能计到59.99s，并用数码管显示计数值。用发光二极管显示向分钟的进位信号。-Assume that the system clock to 50MHz, the design of an electronic stopwatch test circuit, so the step by 0.01s to time. The electronic stopwatch

用Verilog实现的单周期CPU,分别实现I型、R型、J型指令，并包含测试文件。可供参考。-With single-cycle CPU Verilog implementation, respectively, to achieve type I, R, J-type instruction, and includes test files. For reference.