搜索资源列表
spi
- VHDL实现SPI功能源代码 -- The SPI bus is a 3 wire bus that in effect links a serial shift -- register between the \"master\" and the \"slave\". Typically both the -- master and slave have an 8 bit shift register so the combined -- register is 16 bits
i211_001
- Dallas 1-Wire ip 非常有用,不占用CPU的时间.
sd_reader.rar
- SD卡读卡器模块的VHDL及软件驱动代码，可作为外设挂接在Avalon总线上。支持以SD模式、4线模式读取。在24MHz时钟驱动下读取速率可达8MByte/s,SD card reader module and software drivers VHDL code, can be articulated as a peripheral bus in Avalon. To support the SD model, 4-wire mode read. Driven by the 24MHz clo
AD9959.rar
- ad9959驱动程序一个串口通信周期分为指令周期和数据读写周期两个阶段。首先传送指令阶段的8位指令字对应于SCLK的8个上升沿,然后执行由指令设定的1～4个字节的数据读写,完成后再等待下一个指令周期的到来。,AD9959 Driver Single-bit serial 2-wire mode
i2c-verilog
- 可进行i2c读写操作I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data exchange between devices. It is most suitable-it can write and read codes in i2c.I2C is a two-wire, bi-directional serial bus that provides a
dallas_one-wire
- dallas one wire的VHDL实现方式,比较常用的.-dallas one wire to achieve the VHDL approach commonly used.
i2c_specs
- I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data exchange between devices.
80C51_1
- 1.异步通信软件模拟2.基于RS-232的串口通信3.基于RS-485的多机通信4. I2C总线协议的软件实现5. SPI总线在单片机系统中的实现6.-wire-1. Asynchronous communication software simulation 2. Based on the RS-232 serial communication 3. Based on the RS-485 Multi-machine communication 4. I2C bus protocol soft
DHT22_v1.1
- 我以前曾发过V1.0版的，这是此版的修正版v1.1,修正了以前版本中的一个错误，即只能读一个数据后就再也读不出温度数据的错误。 这个是用Quartus II软件写的Verilog HDL语言写的与温湿度传感器DHT2x通信的代码. 里面有详细的注解. 主要用于DHT2x单线总线通信转换为8位并行总线通信,应用于具有外部8位总线访问功能的单片机直接读取温湿度数据. 此程序在EPM7128SLC-10中成功测试. -I' ve once spoke V1.0 version, whic
XilinxOneWireInterface
- Xilinx公司的1 wire接口HDL源代码，可以用来读取1 wire的rom。-Xilinx Inc. 1 wire interface to HDL source code, can be used to read the 1 wire in the rom.
Solutions
- `timescale 1ns / 1ps module AND_OR(INP, OUT1) input [3:0] INP output OUT1 wire SIG1, SIG2 MY_AND2 U0 (.A(INP[0]), .B(INP[1]), .C(SIG1)) MY_AND2 U1 (.A(INP[2]), .B(INP[3]), .C(SIG2)) MY_OR2 U2 (.A(SIG1), .B(SIG2), .
SRAM_controller_of_FPGA
- 视频处理源码，使用pdf格式输出，用的时候自解压，然后拷贝黏贴就行了。-`timescale 1ns/1ns module asyn_fifo(clk_wr,wr_en,clk_rd,rd_en,rst,din,full,empty,dout) input clk_wr,wr_en,clk_rd,rd_en,rst input[7:0] din output full,empty output[7:0] dout reg full_temp,empty_temp
spi_master_0716
- 关于四线制SPI电路verilog代码设计，支持Avalon总线-About four-wire SPI circuit verilog code design, support Avalon bus
ds1wm
- DS1WM master for controlling one wire devices like DS18B20
an483
- The Altera® Triple Speed Ethernet (TSE) data path reference design provides a sample SOPC Builder system using the Altera TSE MegaCore® function with two serial transceivers. This reference design demonstrates the operation of the Alte
opencores_i2c
- I2C 总线协议通过两线串行数据SDA 和串行时钟SCL 线在连接到总线的器件间传递信息,每个器件都有一个唯一的地址识别,而且都可以作为一个发送器或接收器.-Through the two-wire I2C serial bus protocol data SDA and serial clock SCL line is connected to the bus transfer information between devices, each device has a unique addr
reg-a-wire
- verilog 使用中reg 与 wire 区别及使用方法-verilog using the difference between reg and wire and method of use
Example-4-8
- always模块的敏感表为电平敏感信号的组合逻辑电路 这种形式的组合逻辑电路应用非常广泛，如果不考虑代码的复杂性，几乎任何组合逻辑电路都可以用这种方式建模。always模块的敏感表为所有判定条件和输入信号，请读者在使用这种结构描述组合逻辑时，一定要将敏感表写完整。在always模块中可以使用if…else…、case、 for循环等各种RTL关键字结构 assign等语句描述的组合逻辑电路 这种形式的组合逻辑电路适用于描述那些相对简单的组合逻辑，信号一般被定义为wire型，常用
DS18b20
- 本设计采用无ROM的8051作为主控制芯片。8051的接口电路有8155，2732和ADC0809等芯片。8155用于键盘/LED显示器接口，2732可作为8031的外部ROM存储器，ADC0809为温度测量电路的输入接口。 本设计温度控制电路是通过可控硅调功器实现的。双向可控硅管和加热丝串联接在交流220V，50HZ交流市电回路，在给定周期内，8031只要改变可控硅管的接通时间便可改变加热丝功率，以达到调节温度的目的。 -This design uses no ROM 8051 as
Reg-vs-Wire
- This book explains about difference between REG and WIRE in Verilog.