搜索资源列表
linaro_demo
- 基于ZNYQ开发板的测试demo，包含linaro操作系统。-Based on zynq-7000 board，the demo project with linaro-linux os。
HelloZynq
- 基于ZYNQ-7000开发板的helloword project，已经配置开发板信息，可运行在14.4ISE环境下。-Based on zynq-7000 helloworld project with essential configuration information，run in ISE14.4
fpgahdl_xilinx-edk.tar
- xilinx zynq 7000 FPGA demo-xilinx zynq 7000 FPGA demo
the-zynq-book-tutorial-sources
- 一本关于赛灵思Zynq-7000 All Programmable（SoC）的书，是由一群来自英国格拉斯哥斯特拉斯克莱德大学（University of Strathclyde）的作者编撰，并得到了赛灵思的支持，书的作者想打造一本易懂可读的读本，让那些刚刚开始接触Zynq和已经在用Zynq的工程师从中受益，并成为工程师们手头的开发圣经。 本书的配套源代码- A book on the Xilinx Zynq-7000 All Programmable (SoC) book by a gr
zynq_IP
- 这是德致伦公司培训 zynq 7000系列的一个经典例子，是关于自定义挂载核的VGA接口-this is a example for ZYNQ 7000
UG586-7SeriesDMIUserGuide
- UG586 - Zynq-7000 All Programmable SoC and 7 Series Devices Memory Interface Solutions v2.3 User Guide ( ver2.3, 18511 KB )-UG586- Zynq-7000 All Programmable SoC and 7 Series Devices Memory Interface Solutions v2.3 User Guide ( ver2.3, 18511 KB )
xapp1082-zynq-eth
- PS and PL Ethernet Performance and Jumbo Frame Support with PL Ethernet in the Zynq-7000 AP SoC 是学习Vivado 入门文档，源自xilinx，权威易懂 -PS and PL Ethernet Performance and Jumbo Frame Support with PL Ethernet in the Zynq-7000 AP SoC Learning Vivado entr
PWM_IP_test
- zynq-7000开发板 PWM IP核（VHDL和Verilog）-zynq-7000 PWM IP
Zynq-7000-for-Hardware-Engineers
- Zynq-7000硬件工程师step by step教程-Zynq-7000 Extensible Processing Platform Design Workshop for Hardware Engineers
Zynq-7000-for-Software-Engineers
- Zynq-7000软件工程师step by step教程-Zynq-7000 Extensible Processing Platform Design Workshop for Software Engineers
rtc.tar
- zynq rtc例程 测试好使的，非常好用，可供参考(zynq rtc program,have been verified)
Z-turn-examples-master
- # Z-turn-examples The repository with my simple Z-turn examples, to be used as templates for more serious projects. Please note, that the Buildroot configuration in my designs sets the root password to "test". Setting the password is n
axi_ipif_v2.3
- The AXI4-Lite IP Interface (IPIF) is a part of the Xilinx family of Advanced RISC Machine (ARM) Advanced Microcontroller Bus Architecture (AMBA) Advanced eXtensible Interface (AXI) control interface compatible products. It provides a point-to-point
AXI-HP-ZYNQ
- 用Vivado IPI搭建的Zynq-7000 PS到PL通信过程，使用了AXI-HP接口，利用AXI-DMA IP实现直接读写DDR的过程，软件可以配置传输尺寸。(The Zynq-7000 PS to PL communication process is built by Vivado IPI. AXI-HP interface is used, and AXI-DMA IP is used to read and write DDR directly. The software can
ug835-vivado-tcl-commands
- Vivado是Xilinx最新的FPGA设计工具，支持7系列以后的FPGA及Zynq 7000的开发。与之前的ISE设计套件相比，Vivado可以说是全新设计的。无论从界面、设置、算法，还是从对使用者思路的要求，都是全新的。看在Vivado上，Tcl已经成为唯一支持的脚本，此文件是vivado是tcl命令的集合。(Vivado is Xilinx's latest FPGA design tool that supports development of FPGAs and Zynq 7000s
ug585-Zynq-7000-TRM
- Xilinx Zynq 7000 参考文档(Xilinx Zynq 7000 Reference documents)
Zynq 7000嵌入式设计官方教程
- zynq7000 嵌入式设计官方教程，学习嵌入式入门书籍(ZYNQ 7000 embedded design official tutorial, learn embedded introductory books)