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fet140_tb_09
- MSP-FET430P140 Demo - Timer_B, PWM TB1-2, Up/Down Mode, DCO SMCLK-MSP-FET430P140 Demo-Timer_B, PWM TB1-2. Up / Down Mode, the making of SMCLK
DCO.rar
- msp430的dco基本程序 里面有11个小程序 使你在最短时间呢对dco的功能做到轻松上手,msp430 basic procedures of dco inside 11 small program allows you to do in the shortest possible time, the function of dco be easy to get started
TA_13
- MSP-FET430P140演示程序。Timer_A PWM TA1-2,模式,SMCLK DCO / / / /描述:这个程序会产生两种PWM输出开P1.2,3使用 / / Timer_A配置的模式。在CCR0价值,512-1,定义了PWM(脉宽调制) / /时间和价值观在CCR1 CCR2 PWM技术和责任周期。利用~ 800千赫 / / SMCLK作为TACLK,定时器周期~ 640我们一个75 的关税P1.2周期, / 25 ,P1.3-MSP-FET430P140
msp430f2619
- 总共包括15种实验源代码，DMA实验 DCO操作实验 硬件乘法器实验 WDT操作实验 16定时器操作实验 I2C通讯操作实验 红外通讯IrDA操作实验 低功耗实验 FLASH实验 UART操作实验等等，是学习MSP430单片机的好例程-A total of 15 kinds of experimental source code DCO operation, the DMA experiment experimental hardware multiplier experimental WDT
fet140_1
- MSP430F Toggle P1.0 by xor ing P1.0 inside of a software loop. // ACLK= n/a, MCLK= SMCLK= default DCO ~800k-MSP430F Toggle P1.0 by xor ing P1.0 inside of a software loop. // ACLK= n/a, MCLK= SMCLK= default DCO ~800k
main
- 中断嵌套。用于13xx 14xx 15xx 16xx系列。 MCLK:DCO ACLK ：32.768K-Interrupt nesting. For 13xx 14xx 15xx 16xx series. MCLK: DCO ACLK: 32.768K
pwm
- msp430g2553// Descr iption: A single sample is made on A10 with reference to internal // 1.5V Vref. Software sets ADC10SC to start sample and conversion - ADC10SC // automatically cleared at EOC. ADC10 internal oscillator/4 times sample // (64x
msp430x20x3_sd16A_01_with_trap_ISR
- MSP430F20x3 Demo - SD16A, Sample A1+ Continuously, Set P1.0 if > 0.3V // // Descr iption: A continuous single-ended sample is made on A1+ using internal // VRef Unipolar output format used. // Inside of SD16 ISR, if A1 > 1/2VRef (0.3V),
main
- 配置时钟为1MHZ,SMCLK默认为DCO频率，应用中断，定时器-Configure the clock to 1 MHZ, SMCLK defaults to DCO frequency, interrupt, timer
msp430g2xx3_wdt_01
- 使用软件定时切换p1 0由WDT ISR。切换率 大约30 ms基于违约DCO / SMCLK时钟源 在本示例中使用的WDT。- Toggle P1.0 using software timed by the WDT ISR. Toggle rate is approximately 30ms based on default DCO/SMCLK clock source used in this example for the WDT.
TimerA_of_MSPF249
- Toggle P1.0 using software and the TA_0 ISR. Timer_A is configured for up mode, thus the timer overflows when TAR counts to CCR0. In this example, CCR0 is loaded with 1000-1. ACLK = TACLK = INCLK = 32768Hz, MCLK = SMCLK = default DCO ~1.045Mhz
SPI_of_MSP430F249
- SPI master talks to SPI slave using 3-wire mode. Incrementing data is sent by the master starting at 0x01. Received data is expected to be same as the previous transmission TXData = RXData-1. USCI RX ISR is used to handle communication with