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PhaseLockedLoop
- This tutorial starts with a simple conceptual model of an analog Phase-Locked Loop (PLL). Through elaboration it ends at a model of an all digital and fixed-point phase-locked loop. The final model can serve a starting point for code generation (both
linkMQ
- 一个简单介绍如何使用Matlab生成HDL代码，如何让使用Matlab和Modlsim联合仿真-A brief introduction how to use the Matlab generated HDL code, and how to make co-simulation using Matlab and the Modlsim
CAD
- Implementation of a parks Macleland filter in Matlab and HDL
simulink-QPSK
- 对QPSK解调系统完美建模，其中通过改变码元速率和载波频率，再计算相应的环路滤波器的参数，即可实现多种QPSK模型的解调，且该模型可通过SYSTEM generator进行量化，从而生成ISE能直接使用的HDL代码。 matlab版本：2007a-Perfect for QPSK demodulation system modeling, which by changing the symbol rate and carrier frequency, and then calculate t
simulink-8PSK
- 对8PSK完美建模，其中通过改变码元速率和载波频率，再计算相应的环路滤波器的参数，即可实现多种QPSK模型的解调，且该模型可通过SYSTEM generator进行量化，从而生成ISE能直接使用的HDL代码。-Perfect modeling of 8PSK, wherein by changing the symbol rate and carrier frequency, and calculate the corresponding parameters of the loop filte
tru
- creating a hdl code generation proj
booth_multiplier
- A classic booth multiplier implemented using verilog HDL using the Xilinx software.
CICFilter
- 一个CIC滤波器的源代码，基于verilog HDL语言(The source code of a CIC filter is based on Verilog HDL language.)