搜索资源列表
i2c(FPGA)
- 基于FPGA的I2C总线模拟，采用verilog HDL语言编写。-FPGA-based I2C bus simulation, using verilog HDL language.
multiply
- 这是我用verilog hdl语言写的浮点乘法器,用的是基4的booth算法,对于部分积使用了5-2压缩和3-2压缩,欢迎大家指点,也欢迎大家把它改成流水线以提高速度.
someccode 象棋之马踏棋盘
- 一些c程序，象棋之马踏棋盘、把算术表达式转化未逆波兰表达式、保龄球计分规则算法、可进行多达50位的大整数运算（＋X）、铁路调度算法，演示了堆栈的基本用法,Some c procedures, horse riding chess board, the arithmetic expressions are not translated into Reverse Polish expression, bowling scoring rules algorithm, can be as many as
cordic_atan
- CORDIC arctangent(atan) Simulink model. You can generate HDL from this model
chinese_version_of_the_gold_reference_for_Verilog.
- Verilog_黄金参考中文版,共HDL开发的朋友使用，要珍惜哦！-Gold reference Verilog_ Chinexe version of Friends of the total development of the use of HDL, it is necessary to cherish Oh!
MQdecoder
- Verilog HDL 实现的JPEG200的MQ解码-JPEG2000 MQ DECODER BASED ON FPGA， Verilog HDL
PhaseLockedLoop
- This tutorial starts with a simple conceptual model of an analog Phase-Locked Loop (PLL). Through elaboration it ends at a model of an all digital and fixed-point phase-locked loop. The final model can serve a starting point for code generation (both
ecc2GUIv091
- EC IMP INCLUDE HDL TEST VEC BENCH , B167, GUI.
hdl
- 对lvds的结构用verilog和vhdl代码进行了详细的描述-The structure of the lvds with verilog and vhdl code described in detail
asias_dds
- 一个简易的信号源，具有多种波形发生功能还有扫频，调制，频率计等相关功能-My project is on Direct Digital Synthesiser using Verilog HDL.This project is doing by me on july 2009 in summer training at NIT Kurukshetra, India. This DDS system generate the square wave, Triangular wave,Sine wa
linkMQ
- 一个简单介绍如何使用Matlab生成HDL代码，如何让使用Matlab和Modlsim联合仿真-A brief introduction how to use the Matlab generated HDL code, and how to make co-simulation using Matlab and the Modlsim
serial_fxptesto
- CORDIC arctangent(atan) Simulink model. You can generate HDL from this model
16-fft-hdl
- 16点fft，其中实现简单，使用的是基4的结构，控制使用状态机-based-16 FFt
CAD
- Implementation of a parks Macleland filter in Matlab and HDL
elevator1_sfun
- 电梯控制模型的搭建,可生成对应的HDL代码-elevator control
1024point-fft--using-verilog-hdl
- 1024点快速傅里叶变换，使用verilog hdl硬件描述语言-1024point FFT，using verilog hdl
robot_7_31
- 使用Verilog HDL来控制机器人，六个高精密舵机，舵机运动非常流畅，舵机不抖动-FPGA to control the robot servo, six servos
div16d8
- 16位除以8位除法器，Verilog HDL语言-16 divided by 8 divider, Verilog HDL language
cordic
- 基于Verilog HDL语言，用cordic算法的旋转模式实现三角函数和反三角函数的计算(Calculation of trigonometric function and anti trigonometric function by rotation mode of CORDIC algorithm)
CICFilter
- 一个CIC滤波器的源代码，基于verilog HDL语言(The source code of a CIC filter is based on Verilog HDL language.)