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cordic_atan
- CORDIC arctangent(atan) Simulink model. You can generate HDL from this model
chinese_version_of_the_gold_reference_for_Verilog.
- Verilog_黄金参考中文版,共HDL开发的朋友使用，要珍惜哦！-Gold reference Verilog_ Chinexe version of Friends of the total development of the use of HDL, it is necessary to cherish Oh!
PhaseLockedLoop
- This tutorial starts with a simple conceptual model of an analog Phase-Locked Loop (PLL). Through elaboration it ends at a model of an all digital and fixed-point phase-locked loop. The final model can serve a starting point for code generation (both
ecc2GUIv091
- EC IMP INCLUDE HDL TEST VEC BENCH , B167, GUI.
linkMQ
- 一个简单介绍如何使用Matlab生成HDL代码，如何让使用Matlab和Modlsim联合仿真-A brief introduction how to use the Matlab generated HDL code, and how to make co-simulation using Matlab and the Modlsim
serial_fxptesto
- CORDIC arctangent(atan) Simulink model. You can generate HDL from this model
CAD
- Implementation of a parks Macleland filter in Matlab and HDL
elevator1_sfun
- 电梯控制模型的搭建,可生成对应的HDL代码-elevator control
simulink-QPSK
- 对QPSK解调系统完美建模，其中通过改变码元速率和载波频率，再计算相应的环路滤波器的参数，即可实现多种QPSK模型的解调，且该模型可通过SYSTEM generator进行量化，从而生成ISE能直接使用的HDL代码。 matlab版本：2007a-Perfect for QPSK demodulation system modeling, which by changing the symbol rate and carrier frequency, and then calculate t
simulink-8PSK
- 对8PSK完美建模，其中通过改变码元速率和载波频率，再计算相应的环路滤波器的参数，即可实现多种QPSK模型的解调，且该模型可通过SYSTEM generator进行量化，从而生成ISE能直接使用的HDL代码。-Perfect modeling of 8PSK, wherein by changing the symbol rate and carrier frequency, and calculate the corresponding parameters of the loop filte
ADPLL
- This paper presents the ADPLL design using Verilog and its implementation on FPGA. ADPLL is designed using Verilog HDL. Xilinx ISE 12.1 Simulator is used for simulating Verilog Code. This paper gives details of the basic blocks of an ADPLL. In this p
tru
- creating a hdl code generation proj
dpd
- 数字预失真处理的主函数，用于修正功放的非线性-power ample digital hdl
CICFilter
- 一个CIC滤波器的源代码，基于verilog HDL语言(The source code of a CIC filter is based on Verilog HDL language.)