搜索资源列表
CORDIC_mixer
- FPGA可实现的，使用cordic算法的NCO模块混频模块。该模块基于cordic原理，算法中只需要加法和移位运算既可以完成信号的混频功能-FPGA can be achieved, the use of the NCO cordic algorithm module mixing module. Cordic module based on the principle, the algorithm only needs Adder and shift operator can complete
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- 請設計一個8位元移位暫存器，規格如下： 當控制線S1，S2輸入為00時，平行載入； 當控制線S1，S2輸入為01時，在一時脈內向右shift 1位元； 當控制線S1，S2輸入為10時，在一時脈內向右shift 2位元； 當控制線S1，S2輸入為11時，在一時脈內向右shift 3位元 -Serial Adder
HaffAdder-in-Wireword-with-Cellular-Automata-in-m
- implementation of 1bit Haff Adder in Silverman Wireword with Cellular Automata in Matlab.
myadder
- adder is the program for adding 2 inputs together
quanjiaqi
- 建立了基于matlab语言的四位全加器仿真模型，通过了系统验证。-Matlab language is established based on four full adder simulation model, verified by the system.
16bit-CLA
- a 16 bit carry look ahead adder verilog code
bitFullAddertesto
- Adder Circuit using Static CMOS
A4_bitFdadas
- Adder Circuit using Static CMOS
trans_sigPnoisePinterference
- 根据直扩原理，首先有随机数发生器产生一系列二进制信息数据（+1，-1），每个信息比特重复Lc次，Lc对应每个信息比特所包含的伪码片数，包含每一比特Lc次重复的序列与另一个随机数发生器产生的PN序列c(n)相乘。然后在该序列上叠加高斯白噪声和形式为i(n)=Acosw0n余弦干扰下次信号，切余弦干扰信号的振幅满足条件A<Lc。在解调器中进行与PN序列的互相关运算，并且将组成各信息比特的Lc个样本进行求和。加法器的输出送到判决器，将信号与门限值0进行比较，确定传送的数据为+1还是-1，计数器用
lms-rls-mlse
- THis transceiver system simulation to display ber vs SNR. TRansceiver is about BER comparison between LMS-RLS and MLSE receiver to invers the rayleigh fading channel. The content of system is modulation, pilot adder, awgn and rayleigh fading channel,
myAdder
- This a simple adder program in matlab-This is a simple adder program in matlab
add16
- designing of 16 bit adder using 4 bit adder using verilog code
GUI-Adder
- MATLAB GUI 实现的一个简单加法器 GUI入门必学-MATLAB GUI Adder for selfstudy
matlabGUI
- 这是一个matlabGUI的基本例程，实现了加法器的功能。可用于matlabGUI入门。-This is a basic routine matlabGUI realized adder function. Can be used to matlabGUI started.
Adder_Subtractor
- this adder subtractor simulation model-this is adder subtractor simulation model
1247900827add
- matlab的GUI实现一个加法器，同时使用mcc编译成了exe的可执行文件，非常适合初学者-matlab GUI implementation is an adder while using mcc compiled into exe executable file, very suitable for beginners
MATLAB-and-Verilog-codes
- there are 5 files. the first two codes are written in Matlab as m-files in control system design to show step responses. in contrast, the final three codes are written in verilog ( Quartus II) used in Altera one of them for BCD adder and the other fo
qam-slicer-and-offset
- qam slicer and offset adder
16x16multiplier
- Design, simulate and synthesize a 16-bit integer multiplier using only one 4-bit adder. This 4-bit adder is to be made with four 1-bit adders as components. The coding is in VHDL.-Design, simulate and synthesize a 16-bit integer multiplier using only
Sigma_Delta_ADD
- Sigma Delta Adder and Corrector, implemented using matlab