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16weijiafaqi
- 本程序是在一位全加器的基础上设计一个16位的加法器,用Verilog HDL语言描述.-This procedure is a full-adder based on the design of a 16-bit adder, using Verilog HDL language to describe.
VGA_LCD
- 这个是VGA显示的硬件电路设计，是用Verilog HDL语言写的，供给硬件电路设计者们去用-This is a VGA display hardware circuit design, is written in Verilog HDL language, the supply of hardware circuit designers to use
Chapter1-5
- 第一章到第五章的代码 本书通过100多个模块实例，详细地讲解了Verilog HDL程序设计语言，全书共分13章，内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等，实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个实例
Examples-from-Verilog-HDL
- 国外经典verilog代码，非常适合初学者自学，同时有些概念老手也可以仔细琢磨琢磨-Foreign classic verilog code, very suitable for beginners self-study, while some of the concept of a veteran can also be carefully pondering pondering. .
control
- 用HDL语言编写的控制单元代码，用于检测SARM是否发生错误的一个拣点小程序。-HDL language of the control unit code, used to detect the SARM whether the error occurred pick a little program.
as1
- Verilong HDL是最frequenctly使用的硬件描述语言，因为它的简单和方便的属性之一。这当然AIMES设计一个数字时钟，配备4段显示，秒表和时间设定使用这种语言，甚至一些额外的功能，fundamatal。 DE1板设计时钟的实施贡献-Verilong HDL is one of the most frequenctly used hardware descr iption language because of its simple and convenient propertie
ug623Libraries-Guide-for-HDL-Designs
- Xilinx 官方 HDL 设计库指导，FPGA设计人员的好帮手-Xilinx HDL design library official guidance, FPGA designers a good helper
A > B gate Verilog HDL
- Just a Code to help with Verilog HDL
frequence
- verilog hdl语言编写，频率测量系统中的一个子单元-verilog hdl Language, frequency measurement system in a sub-unit
clk_gen
- this is a clock generator program by using concurrent language verilog hdl with xilinx ise.
Adder_12bit
- 带进位的12位宽超前进位加法器，可以在工程中直接调用。使用Verilog HDL编写。-A 12-bit wide carry lookahead adder with carry bit, that can be called directly in the project. Written using Verilog HDL.