设计实现4bit FIFO, 数据深度为8， 产生满， 空状态标志-The diagram of FIFO is shown in figure 1. The FIFO consists of two component: FIFO control logic and RAM. The control logic generates the address (ADD) and write enable (WE) to the RAM so that the fi

KEY FEATURES Resolution of 230,000 Counts (Peak-to-Peak) Offset Drift: 5 nV/8C Gain Drift: 2 ppm/8C Line Frequency Rejection: >150 dB Buffered Differential Inputs Programmable Filter Cutoffs Speci Two-Channel Programmable Gain Fron