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PREDICTION.FRACTIONALN.SPURS
- Fast settling-time added to the already conflicting requirements of narrow channel spacing and low phase noise lead to Fractional4 divider techniques for PLL synthesizers. We analyze discrete \"beat-note spurious levels from arbitrary modulus di
plugin-tut_timing_verilog_Lab2
- manual for time analysis and testing the critical path in verilog FPGA using Accumulator design
DDS1
- 直接数字频率合成器（Direct Digital synthesizer）是从相位概念出发直接合成所需波形的一种频率合成技术。一个直接数字频率合成器由相位累加器、加法器、波形存储ROM、D/A转换器和低通滤波器（LPF）构成-Direct digital frequency synthesizer (Direct Digital synthesizer) is the concept of direct synthesis from the requirements phase of a wav
222
- pipelined multiplier accumulator architecture
jia
- 摘要:介绍了利用直接数字合成技术产生频率扫描信 号的新方法。利用计数器和相位累加器实现对波形存 储器寻址, 从而产生频率扫描信号序列。该序列通过 数-模转换器和低通滤波器后, 产生出频率扫描信号。 被合成的频率扫描信号的起始频率、 终止频率和扫描 时间可根据需要随意设定,并且可以实现对三者的精 确控制。-Abstract: The use of direct digital synthesis techniques to create a new method of fr
01-(3)
- 基于单片机8031的太阳能交通警示牌的设计，以太阳能为能源, 给蓄电池加上充、放电保护装置, 防止过充电和过放电。该警示板设置在夜间有事故隐患的路段, 以太 阳能光伏板为传感器的光控电路, 控制LED 在白天关闭、夜间开启。-This design takes the solar energy as the energy, adds on the electric discharge protective device sufficiently to the accumulator ce
architecture-course-design
- 组成原理课程设计 编写应用程序，实现以下功能： 通过机器指令集实现两个二进制数的四则运算。数据通过IN指令输入到A累加器中，输入菜单选项选取运算的方式（1：乘法，2：加法，3：减法，4：除法）。 输入形式：数据输入形式为二进制，第一个数据为第一个运算数，第二个数据为第二个运算数，第三个数据为菜单选项。 输出形式：通过实验箱上的out输出端口显示，显示形式为十六进制数。 实现说明： 乘法：通过循环使用加法实现乘法功能，第二个操作数作为被乘数，对其自身累加，当累加等于第一个操
driver_v3.2
- Led driver for lipo accumulator with firmware C++ source
fpmac-90nm
- A pipe-lined single-precision floating-point multiply accumulator, operations at speeds exceeding 3 GHz with single-cycle throughput, achieves 6.2 G Flops of performance while dissipating 1.2 W at 3.1 GHz, 1.3-V supply.-A pipe-lined single-precisio
main
- My file is about Fetch and Executive stages of processing. The processor contains a single data register, called the accumulator (AC). Both instructions and data are 16 bits long, and memory is organized as a sequence of 16-bit words. The instruction
Architecture-algorithm-joint-exploration-of-Hough
- The Hough transform is a robust algorithm used in shapes and objects recognition and it proves a high quality of results. This algorithm is also known for its use of large computing power. This paper presents a dedicated accumulator cache to
Algorithmic-Evaluation-of-Line-Detection-Problem.
- The Hough transform is a well-established scheme for detecting digital line components in a binary edge image. A key to its success in practice is the notion of voting on an accumulator array in the parameter plane. This paper discusses computati