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trafficlight
- 基于quartus 6.0的课设设计，非源码，系统设计方案-Quartus 6.0 based on the design of the class-based, non-source, system design
FPGAdeguangshanjiancejishu
- 本文档设计了1光栅位移传感器信号的接收、光栅位移传感器信号的整形及电平转换电路设计，用Verilog HDL描述了锁相倍频细分和零位信号处理电路。利用FPGA实现光栅位移系统与上位机接口的电路原理框图-This document designed a grating displacement sensor signal reception, grating displacement sensor signal shaping and level conversion circuit design
syn_fifo
- 基于systemverilog的异步fifo-fifo of design ，system verilog
verilog
- 文档给出了verilog数字系统设计的6个实践项目的详细设计过程，包括设计思路、顶层设计和各个模块设计的源码和详细说明-The document gives 6 verilog digital system design practice project detailed design process, including source code and a detailed descr iption of the design ideas, the top-level design and m
Counter_AD
- Parametrized System Verilog code for a Counter with an increade, decrease switch (AD)
BCD_7Segmentos
- System Verilog code to send BCD values to 7 segments displays
DetectorDeSigno
- System Verilog sign detector module if number its negative, gets a2 compliments drops the value and a flag
Decodificador
- System Verilog decodificator. Enters a value(binary), drops hundreds, tens and units in BCD
Clk_Divider
- System Verilog Clock Divider module done with impementation, contains the implementes modules inside too.
ModportInterface
- Example of how to use Modport in System Verilog.
sva2_toc_preface
- system verilog assertion handbook 2nd edition
SV_UVM_fr
- system verilog with universal verification methodology
Course-Materials
- it is system verilog simple program program based on classe
SVVQ
- System verilog questions
Verilog-DS18B20
- 这是个基于VERILOG的温度采集系统的源程序文档-This is based on the temperature acquisition system VERILOG source document
systemverilog
- 是关于System Verilog的课件，简要介绍了了System Verilog的用法，主要介绍进行可仿真和可综合的硬件设计，作为Verilog的扩展，在抽象设计、测试平台和基于C语言的应用程序设计接口有重大改进。-About System Verilog courseware, brief introduction of System Verilog usage introduces conduct can be integrated simulation and hardware desi
verilog
- verilog常用系统函数及例子，包含一些经常会用到的小程序例子及系统函数。-verilog common system functions and examples, including some often used a small program examples and system functions.
SHIFT-RESISTER.tar
- its about a shift register design using verilog and verification using system verilog files for uvm.
Online-Shopping-System-project-Source-code
- In this homework, you will need to compile and simulate a System Verilog program (constraint_mode_ex.sv) which implements multiple constrained-random test. A more detailed descr iption of the program can be found below:
System-Verilog-Introduction
- system Verilog introduction