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Virtex.files
- 在FPGA系统设计中，要达到性能最大化需要平衡具有混合性能效率的元器件，包括逻辑构造(fabric)、片上存储器、DSP和I/O带宽。在本文中，我将向你解释怎样能在追求更高系统级性能的过程中受益于Xilinx® 的Virtex™ -5 FPGA构建模块，特别是新的ExpressFabric™ 技术。以针对逻辑和算术功能的量化预期性能改进为例，我将探究ExpressFabric架构的主要功能。基于实际客户设计的基准将说明Virtex-5ExpressFabric技术性能平
PCICOREGUIDE
- 本指南讲述支持的基于 Virtex™ 和 Spartan™ 架构的 32 位和 64 位核的设计流程，并且介绍 Cadence® IUS v5.8 中的示例设计。-This guide based on the support of the Virtex ™ and Spartan ™ architecture 32-bit and 64-core design process, and Cadence ® IUS v5.8 intr
FPGA_DSP
- Virtex-II Pro _ Virtex-II Pro X 完整数据手册(包含全部4个模块)；XtremeDSP开发套件Pro用户指南；及如何利用ML300 Virtex-II Pro开发系统着手开始搭建系统。-Virtex-II Pro _ Virtex-II Pro X Full Data Sheet (includes all four modules) XtremeDSP Development Kit Pro User Guide and how to use the ML30
VHDL_RAM
- Virtex II pro RAM memory
VHDL_UART
- Virtex II pro UART RS232
VHDL_VGA
- Virtex II pro VGA control
pBlazIDE36
- There are literally dozens of 8-bit microcontroller architectures and instruction sets.Modern FPGAs can efficiently implement practically any 8-bit microcontroller, and available FPGA soft cores support popular instruction sets such as
DesignandFPGAImplementationof
- In most cases, a bandpass filter characteristic is obtained by using a lowpass-to-bandpass frequency transformation on a known lowpass transfer function. This frequency transformation controls the location of passband edges and transfer zero
FPGAIMPLEMENTATIONOFATUNABLEBANDPASSFILTER
- Any Band-Pass filter may be converted into a tunable filter with a single tuning parameter through the use of a new Tunable Heterodyne Band-Pass Filter concept in which the frequency of the heterodyne signal is adjusted thereby translating the
GeneratingFPGA-AcceleratedDFTLibraries
- 关于DFT的文章，应用FPGA实现傅立叶变换。-Abstract—We present a domain-specific approach to generate high-performance hardware-software partitioned implementations of the discrete Fourier transform (DFT). The partitioning strategy is a heuristic based on the DFT
DDR2deFPGAsheji
- 使用 Virtex-4 FPGA 器件实现DDR SDRAM控制器以及DDR2 SDRAM操作时序-Using the Virtex-4 FPGA devices to achieve DDR SDRAM and DDR2 SDRAM controller operation timing
MicroBlaze-and-PowerPC
- Virtex 5系列的硬核和软核描述 -Virtex 5 series of hard-core and soft-core descr iption
ML505_Overview_Setup_2010
- virtex 5操作说明书，里面详细的说明了每一步操作-virtex 5 operation manual, which explains in detail every step of the operation
Virtex-5-
- 好用的Virtex-5 开发板与套件，基于fpga的嵌入式开发平台-Easy to use Virtex-5 development board with a package based on fpga' s embedded development platform
Virtex-5
- Detail descr iption about virtex 5
c_ds150
- Xilinx Virtex-6系列电气特性的中文概述-Xilinx Virtex-6 Series Electrical Characteristics of Chinese Overview
xapp882
- This application note describes the implementation of SERDES Framer Interface Level 5 (SFI-5) [Ref 1] in a Virtex-6 XC6VLX240T FPGA. SFI-5 is a standard defined by the Optical Internetworking Forum (OIF). The interface must operate bidirectionall
Virtex5-datasheet-
- VIRTEX开发必须的中文文档，非常适合初学者和学习xilinx原语的同志学习-VIRTEX development must the Chinese documents, very suitable for beginners to learn and learn from Comrade xilinx primitives
GenesysGeneral-ucf
- Genesys™ Virtex-5 FPGA Development Board用户约束文件，来自官方LX50T板子-Genesys™ Virtex-5 FPGA Development Board Genesys--VIP GenesysGeneral-ucf.zip
ddrpspsbf
- 基于FPGA的雷达脉冲预分选器设计--这里, 提出一种基于关联比较器的雷达信 号分选方法,在实现多参数分选的同时, 也保证了实时性。详细阐述了在 Virtex 4 系列 FPGA 上实现基于内容可寻存储器 ( CAM)的关联比较器的途径。-Design of Radar Pulse Signal Pre-sorting Based on FPGA