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Xilinx
- XILINX大讲堂、十招加速Vivado IPI设计、Vivado HLS 中指针作为top 函数参数的处理、Vivado HLS 中的浮点设计编码风格与技巧、编写高效Vivado HLS 工程testbench 的三个要素-XILINX auditorium, ten strokes accelerate Vivado IPI design, Vivado HLS deal with top pointer as function parameters, Vivado HLS floating
Vivado_debug_to_MATLAB_doc
- 介绍了Xilinx Vivado debug调试环境下，将调试数据导入MATLAB的方法，简单易用，欢迎交流-Guide for Xilinx Vivado debug, import data to matlab.
ug902-vivado-high-level-synthesis
- Xilinx Vivado HLS 高层次综合工具的用户手册-User manual for Vivado HLS Xilinx high level synthesis tools
DDR3_ip
- 本文档开发环境为vivado软件，描述了ddr3 IP core的生成过程，亲测可行。-this document describe ddr3 ip core genetator process.I test it by myself.
IP
- 如何快速在Vivado IPI中使用HLS生成的IP-How to fast in IPI IP using HLS generated Vivado
vivado_jian_ming_jiao_cheng_
- Vivado中文使用教程,详细介绍了XILIN开发工具vivado的使用方法.-Vivado Chinese design manual
license
- LICENSE FOR VIVADO , please try, very good I think
AXI-54
- this all about viviado AXI four light bus communication. it is good for every one who is intersted in studying vivado axi light interfacing-this is all about viviado AXI four light bus communication. it is good for every one who is intersted in study
Assignment-02-1
- this all about viviado AXI four light bus communication. it is good for every one who is intersted in studying vivado axi light interfacing-this is all about viviado AXI four light bus communication. it is good for every one who is intersted in study