此文件为msp430 ad库文件，可用于画原理图等

This VERILOG simulation example shows a 16 bit group ripple adder circuit for FPGA. The netlabel is used to split 16 bit bus to four 4 bit bus and connect them to four 4 bit adder. The result is joined to a 16 bit bus using netlabel. The Simulation c

Altium Designer 16基础实例教程（附微课视频）-PPT(Altium Designer 16-PPT)