当前位置：
首页 资源下载
搜索资源 - formal verification
搜索资源列表
-
0下载：
学生注册— 本模块允许新的学生创建和维护他们的帐户信息，帐户信息包括：first name, last name, address, e-mail, login name, and password
学生验证— 本模块处理学生的登录过程，像验证用户名和口令，这可以确保仅有已注册的学习可以浏览课程目录和注册课程。
课程目录浏览— 本模块由Web site显示学校当前提供的课程和他们的 细节，课程细节包括课程名和费用
注册购物车— 本模块允许学生在浏览课程目录中将选择的
-
-
0下载：
主要功能说明：
1.用口令（密码）形式验证管理员身份（可输入三次），合法者可进入，否则程序结束。
2.有关功能说明
1）建立学生成绩表（模块a）
建立新的学生成绩文件；
建立若干学生记录，包括姓名、学号、班级、课程编号、成绩。
2）添加学生记录（模块b）
在已存在的学生成绩文件中添加新记录。
3）删除学生记录（模块c)
在学生成绩文件中删除有三门课程不及格的学生记录；
删除前，逐条显示符合删除条件的学生姓名、成绩，确认后
-
-
0下载：
其中，Verilog硬件描述语言（HDL）的定义，在这个标准。 Verilog的HDL是一个正式的符号中的电子系统创建的各个阶段使用。因为它既是机读和人类可读的，它支持开发，验证，综合，硬件设计和测试，对数据通信的硬件设计，以及维修，改装和硬件采购。这个标准的主要对象是工具的实现者支持的语言和语言的高级用户。-The Verilog Hardware Descr iption Language (HDL) is defined in this standard. Verilog HDL is a
-
-
0下载：
wifi rural extantion
Formal Specification and Verification of WiFiRe protocol related pdf file
-
-
0下载：
用做定理证明、推理。可以扩展，比如与Z specification结合使用，做后期的verification。这个软件是软件工程学中formal method的一个很好的代表。-Isabelle is a generic proof assistant. It allows mathematical formulas to be expressed in a formal language and provides tools for proving those formulas in a lo
-
-
0下载：
Improve design efficiency and reduce costs with this practical guide to formal and
simulation-based functional verification. Giving you a theoretical and practical
understanding of the key issues involved, expert authors explain both formal
tec
-
-
1下载：
7:1LVDS编码 为LVDS方面需求的人提供参考设计，很高兴- This VHDL or Verilog source code is intended as a design reference which illustrates how these types of functions can be implemented.
It is the user s responsibility to verify their design for
consistency a
-
-
0下载：
Rebeca模型硬件设计形式化验证Rebeca model for formal verification of hardware design-Rebeca model for formal verification of hardware design
-
-
0下载：
分析：制定规范
设计：状态图，真值表，编写代码。
验证：证明电路的正确性。仿真和形式化验
证。
综合：高层次到低层次转换。生成网表
测试：发现废品。生成测试向量-Analysis: norm design: state diagram, truth table, write the code. Authentication: proof of the c
-
-
0下载：
Formal verification of Cayley s representation theorem in Isabelle/HOL
-
-
0下载：
How can we determine the added value of software verification
techniques over the more readily available conventional testing
techniques? Formal verification techniques introduce both added
costs and potential benefits. Can we show objectively
-
-
0下载：
This VHDL or Verilog source code is intended as a design reference
// which illustrates how these types of functions can be implemented.
// It is the user s responsibility to verify their design for
// consistency and functionality through the
-
-
0下载：
This VHDL or Verilog source code is intended as a design reference
// which illustrates how these types of functions can be implemented.
// It is the user s responsibility to verify their design for
// consistency and functionality through the
-
-
0下载：
This VHDL or Verilog source code is intended as a design reference
// which illustrates how these types of functions can be implemented.
// It is the user s responsibility to verify their design for
// consistency and functionality through the
-
-
0下载：
Formal analaysis and verification of an OFDM modem design
-
-
0下载：
Symbolic logic generally supports the reasoning with propositions, i.e., with statements to be evaluated to true or false. Temporal logic is a special branch of symbolic logic focusing on propositions whose truth values depend on time.
-
-
0下载：
Formal verification of analog and mixed signal designs A survey
-
-
0下载：
formal verification -> verification hardware
-
-
0下载：
// --- --- --- --- --- --- --- --- --- --- --- --
// Copyright (c) 2007 by Terasic Technologies Inc.
// --------------------------------------------------------------------
//
// Permission:
//
// Terasic grants permission to use and mod
-
-
1下载：
现在最流行的RTL设计方法之一，本书为全球流行的设计入门书籍(One of the most popular RTL design methods nowadays, this book is an introductory book for popular design all over the world.)
-
