资源列表
ref-ddr-sdram-vhdl
- 用VHDL编写DDR SDRAM Controller的源代码- Compiles DDR SDRAM Controller with VHDL the source code
16位乘法器
- 自已写的一个16X16的乘法器，速度比较慢。初学者练习练习！-own writing an audio Multiplier, speed is relatively slow. Beginners practice practice!
能综合的YCrCb2RGB模块（verilog)_采用3级流水线
- 能综合的YCrCb2RGB模块（verilog)_采用3级流水线,用fpga做小数运算，还有就是流水线技术 -can YCrCb2RGB integrated module (Verilog) _ used three lines, they simply do with fractional arithmetic, there is pipelining technology
自定义逻辑PWM的例子
- 是一个用vhdl语言编写的pwm程序，可以方便地用来和nios连接，实现对nios的功能扩展。-is a VHDL language with the PWM procedures can be used to facilitate connections and nios, nios to achieve a functional extension.
ref-sdr-sdram-vhdl
- DDR控制器的VHDL源代码.采用FPGA实现DDR接口控制器,适用于Altera的FPGA,最高频率可到100M-DDR controller VHDL source code. Using FPGA DDR interface controller, applicable to Altera FPGA, the highest frequency available 100M
PINPAN
- 乒乓游戏 ，led流水灯控制乒乓球，按键控制甲方已方操作。详细说明看readme-ping-pong game, led lights to control water table tennis, has been chosen to control keys to operate. Details see readme
8位相位相加乘法器
- 8位相 加乘法器，具有高速，占用资源较少的优点-eight multiplier phase together with high-speed, taking up less resources advantages
altera的IP源码
- Altera的IP源码8259，只需打开就能实现-Altera IP source 8259, will be realized only open
CORDIC
- 用verilog写的CORDIC算法实现，很适合做超越函数的运算。通常用于实现正弦乘法，或者坐标变换。-The cordic arithmetic implemented by verilog is adapted to exceed function.It is usually used to implement sine multiplication or coordinate tuansform.
七段码显示串口接收数据
- 在wince6.0上运行，使用PC104可以将串口接收到的数据存成文件，同时将实时数据以七段码的形式显示在屏幕上