资源列表
16QAM
- 基于FPGA 16QAM解调verilog代码，-16QAMdemoluator veriliog
SDRAM_ipcore_
- Altera SDRAM ip核详解-Altera SDRAM ip nuclear Detailed
TLC2543
- 使用Verilog实现的AD采样，很有用的！-Implemented using Verilog AD sampling, very useful!
PIPE_LINING_CPU_TEAM_24
- 采用Quatus II编译环境，使用Verilog HDL语言编写实现了五段流水线CPU。 能够完成以下二十二条指令（均不考虑虚拟地址和Cache，并且默认为小端方式）： add rd,rs,rt addu rd,rs,rt addi rt,rs,imm addiu rt,rs,imm sub rd,rs,rt subu rd,rs,rt nor rd,rs,rt xori rt,rs,imm clo rd,rs clz rd,rs slt rd,rs,rt sltu rd,
Verilog-float-mutiplier
- 32位浮点型乘法器，和开方器,很有用的一种，就是认真读懂-32 float mutiplier
usb_phy.tar
- Very simple USB 1.1 PHY. Includes all the goodies: serial/parallel conversion, bit stuffing/unstuffing, NRZI encoding decoding. Uses a simplified UTMI interface. Currently doesn t do any error checking in the RX section [should probably check f
ssram
- 同步静态RAM读写程序，可用作模块，已通过ISE12.4验证-Synchronous Static RAM read and write procedures, can be used as modules, have been verified by ISE12.4
caiheng
- 利用Verilog实现32位浮点数的乘法,并且已通过验证.-Using Verilog to achieve 32-bit floating point multiplication, and has been verified.
dpll
- dpll的verilog代码，完成数字锁相。用于时钟对准，位同步。-dpll the verilog code to complete the digital phase-locked. Alignment for the clock, bit synchronization.
SHFRT4_1
- 四位串入并出移位寄存器,实现串并转换,已通过时序验证-Four series in and out of shift register, to achieve string and conversion, has passed the timing verification
CY7C68013_DEMO
- cy7c68013原理图和程序 实现fpga和68013通信程序代码-Cy7c68013 principle chart and procedures To realize the fpga and 68013 communication program code
dac
- 基于FPGA实现对DA芯片的控制，以及时序的编写-FPGA control to DA chip