资源列表
pll
- 用VERILOG语言实现的数字锁相环P-VERILOG language with the digital phase-locked loop PLL
YCbCr2RGB
- verilog 实现的YCbCr到RGB得转换-verilog implementation YCbCr to RGB was converted
USB2.0
- usb2.0 fpga程序 用vhdl语言编写 quartus环境实现 -usb2.0 fpga using vhdl language program quartus environment to achieve
ISE_lab19
- 俄罗斯方块VHDL实现，。该设计由下面模块组成：键盘输入模块，游戏控制模块，图像显示模块，文字显示模块，存储单元，复用单元和VGA 控制模块组成。其中图像显示模块和文字显示模块复用VGA 控制模块。游戏控制模块，图像显示模块和文字显示模块通过存储单元交换数据。-Tetris VHDL implementation. The design consists of the following modules: Keyboard input module, the game control modul
1
- 基于matlab和QuartusII开发的无线通信FPGA设计,内有(matlab代码,Verilog代码,缩略语表.doc)注释详细,代码数十个,总有一个是你喜欢的!-Matlab and QuartusII based on the development of wireless communications FPGA design, there are (matlab code, Verilog code abbreviations. Doc) Notes detail dozens of
NCO_based_rom
- 完整的基于ROM查找表的NCO 产生10位宽的正交信号-Integrity of the ROM-based lookup table of the NCO have 10-bit wide of the orthogonal signal
xilinxfpga_jtag
- XilinxUSB EEPROM是xilinx usb下载线的EEPROM程序，可以用来做xilinx的usb下载线-XilinxUSB EEPROM is xilinx usb download cable in the EEPROM program can be used to make the usb xilinx download cable
Core8051
- VERILOG编写的Core8051实验例程，包括整个工程，周立功公司提供-VERILOG Core8051 written test routines, including the entire project, provided ZLG
cic
- altera 公司 quartusII 提供的cic ip ,文件版本是8.0-altera company quartusII provided cic ip, file version is 8.0
nnARM_core
- nnARM核源代码,用verilog编写,请需要的朋友下来研究,不要用于商业用途-nnARM core source code, using verilog write, please study the needs of a friend down, not for commercial purposes
ALU
- ALU与ALU控制器设计，verlog语言书写-ALU
mult
- 16位乘法器,输入16位乘数，输出32位积，采用循环移位算法-a multplier