资源列表
prbs
- 高速并行数据伪随机化模块，包括发送侧的随机化和接收侧的去随机化，以及测试模块-High-speed parallel pseudo-random data modules, including randomized and receive side of sending side to randomization, and the test module
m_seq
- 用VHDL代码编写的m序列发生器，包含发生器和测试用例模块-M sequence generator written in VHDL code, including the generator and the test case module
qpsk
- 用ISE10.1 实现的简单qpsk功能实验-qpsk lab achviment
FPGA_control_ADF7021
- 用FPGA控制射频芯片ADF7021的Verilog程序-Verilog program the FPGA to control the RF chip ADF7021
IIs_interface_v4
- IIs接口的Verilog程序，此接口用于传输语音数据，程序好用-IIs interface Verilog programs, this interface is used to transmit voice and data, easy to use program
Multiplier16
- 本文设计了一种可以实现16位有符号/无符号二进制数乘法的乘法器。该乘法器采用了补码一位乘（Booth算法), 简化了部分积的数目, 减少了某些加法运算,从而提高了运算速度。该乘法器利用Verilog代码实现，通过Modelsim软件对相应的波形进行仿真验证，并通过QuartusII软件对源码进行编译综合。-This paper designed a 16 signed/unsigned binary number multiplication of the multiplier can be a
mult_16
- 这是自己设计的16位乘法器设计，其中用了booth编码，，4-2压缩器等，-This is a 16 multiplier design of their own design, including the booth encoding 4-2 compression, etc.,
EtherCAT_IPCore_Xilinl
- EtherCAT从站控制器芯片ET1817及其IP_Core应用-EtherCAT Slave Controller IP Core for Xilinx FPGAs
CCD
- 以E2V的CCD芯片为核心的图像采集显示系统，其中包括AD采样，基于SRAM的乒乓操作，PAL制式的显示，有兴趣的高手还可以在此基础上进行图像处理。-CCD,image display,AD,SRAM,PAL,image processing
fpga-uart
- 基于DE2开发板的串口通信程序，使用Verilog HDL语言，-Serial communication program based on the DE2 board, using the Verilog HDL language
AD
- AD的行为级模型，10位的，并行输出，已验证过了，比较稳定-Behavioral models of AD 10, the parallel output has been verified, and is relatively stable
FIR
- 基于FPGA的1000阶FIR数字滤波器-1000 order FIR digital filters based on FPGA