资源列表
fet440_ta_pwm01
- MSP-FET430P440 Demo - Timer_A PWM TA1-2 upmode, DCO SMCLK-MSP-FET430P440 Demo-Timer_A PWM TA1-2 up mode, the making of SMCLK
commumdemo
- 一个关于通信的例子，我自己写的，希望可以对大家又帮助-a communication on the case, I wrote it myself, we want to be helped
targetss
- header file of the specific codes for LPC2100 target boards -header file of the specific codes for LPC21 00 target boards
Modem_1
- 串行，并行MODEM 的实例 串行，并行MODEM 的实例-serial, parallel, serial modem example, parallel examples MODEM
1602
- 凌阳1602液晶显示器驱动。IOA高8接数据 IOB8～10接RS、RW、E
trafficcontrol
- 十字路口交通控制器,主,支路的交通灯控制,带左拐的信号灯.
AD9850-Si.rar
- 单片机应用 c语言编写 注释详细 基于AD9850的数字信号发生器,Single-chip Microcomputer Application Notes details c language based on the AD9850 digital signal generator
noINTR
- MikroC source code to control a robot. Uses PIC microcontroller
chap5_03_PP_STC_Direct
- 极点配置间接自校正控制（最小相位确定系统） 在实际通信系统仿真过程中非常有用-Poles from indirect calibration control (minimum phase sure system) In the actual communication system simulation process is very useful
stack_16x8
- VHDL语言写的16x8堆栈模块设计，存储器全满时给出信号并拒绝继续存入；读出时按后进先出原则；存储数据一旦读出就从存储器中消失；有相应的testbech文件，经测试可用。对小型设计很有用！欢迎下载交流学习。-Write VHDL 16x8 stack module design, memory signal is given full and refused to continue the deposit readout LIFO principle store data read out
verilog
- 全数字锁相环的verilog源代码，用于FPGA开发全数字锁相环-DPLL verilog source code for FPGA development DPLL
pci1
- 如果想为了以后的2k平台兼容就最好编wdm，因为windows2k不支持vxd，而且以后的发展wdm肯定要代替vxd了。不过由于我找到的资料基本上都是介绍vxd的，感觉vxd的技术好像更成熟一点，编的人更多一点，所以偷了一下懒（惭愧），就没有去研究wdm，就选择了vxd。-If you want to later edit 2k on the best platform compatible wdm, because windows2k not support vxd, wdm and futu