资源列表
opensslForARM.Makefile.rar
- 生成openssl for ARM的库时,openssl的MAKEFILE所需的补丁文件,Openssl for ARM to generate the library, openssl patch required for the MAKEFILE file
light
- 51实现交通灯控制,可以用于学习发光二极管的用法,也可以直接用于工业设计!是不可多得的源码!-51 to achieve traffic light control, can be used to study the use of light-emitting diodes can also be directly used for industrial design! Is a rare source!
jtd
- 第一个状态：主干道、支干道均亮红灯5S * *第二个状态：主干道亮绿灯30S、支干道亮红灯 * *第三个状态：主干道绿灯闪3次转亮黄灯、支干道亮红灯3S * *第四个状态：主干道亮红灯、支干道亮绿灯25S * *第五个状态：主干道亮红灯、支干道绿灯闪3次转亮黄灯3S * *返回到第二个状态-The first state: trunk, branch roads are red second 5S** state: a green light trunk 30S, branc
li_vcARMmodel
- 由AR模型参数得到功率谱，吐血推荐，需要的用户请下载-AR model parameters obtained from the power spectrum, hematemesis recommended, users need to download
Nethaji_MB
- Ho, this is motion blur restoration algorithm in matlab
selectday
- JAVA语言。请输入星期几的第一个字母来判断一下是星期几，如果第一个字母一样，则继续 判断第二个字母。-JAVA language. Enter the first letter of a few weeks to determine what day of the week, if the first letter of the same, then continue to determine the second letter.
adder16_2
- 16位2级流水线加法器的Verilog设计-16 2 pipeline adder Verilog Design
transpose_buffer
- verilog source code for transpose buffer 8x8 matrics
testmult_top
- TESTBENCH测试程序，小数加法器的实现，小数位设为2位，将其小数位与整数位分别显示出来。-TESTBENCH test procedures, the implementation of decimal adder, is set to two decimal places, its decimal places, respectively, with the integer-bit display.
FIR
- 10阶的F.I.R滤波器设计的 verilog代码-Verilog code for the 10-order FIR filter design
div
- 两个3位二进制数的除法，结果（整数商）输出到数码管显示-verilog multply
ram
- vhdl code for simple ram block