资源列表
Freq_Divider
- frequency divider fpga get slow frequency
sn7448
- verilog实现的“BCD/七段译码器”。-verilog implementation " BCD/Seven-Segment Decoder."
fifo.v
- This the source code for FIFO -This is the source code for FIFO
subtractor
- Verilog source code for full subtractor module build with predefined nor gates.
install-vxworks62-xscale
- install txt for vxworks 6.2 intel-xscale license文件-install txt for vxworks 6.2 intel-xscale license
divider
- Verilog语言编写分频器，用于数字竞赛式抢答器的设计模块之一-The Verilog language divider for digital contest Responder design module one
Decade-Counter
- decade counter with two input and count out outputs
vbSANLINGPLC
- vb与三菱PLC通信,这个也是很不错的东西，推荐一下-vb with Mitsubishi PLC communication, this is also a very good thing, recommend
ssd1306
- solomon ssd1306 驱动源代码-solomon ssd1306
sqrt
- 用verilog实现的开2次方，已经在modelism中经过验证，其时间周期不固定。-Implementation open square with verilog.
binbcd8
- Binary to BCD conversion in VHDL for implementation in FPGA
8051-bt
- 8051接收藍牙與接收的初始設定 1/12T的8051改24MHz,要改TH1-8051 receiving Bluetooth