资源列表
22
- 使用VHDL实现16进制的计数器的算法程序-Use VHDL to achieve 16 of the counter-band algorithm procedure
SRDFF
- Zip file contains the shiftregister code using verilog HDL
key-dejitter
- 按键去抖模块，避免按键抖动引起的系统误操作。FPGA时钟频率25.000MHZ-Key de-jittering module to avoid system misoperation caused by key-jitter. FPGA clock frequency 25.000MHZ
5renduoshuVHDL
- 5人多数表决VHDL源代码，数码管可以显示倒计时时间和通过的人数-5 Most of the voting machine
VHDL1
- 4位并行加法器，a3,a2,a1,a0,b3,b2,b1,b0,cin为输入，cout,s3,s2,s1,s0为输出-4-bit parallel adder, a3, a2, a1, a0, b3, b2, b1, b0, cin as the input, cout, s3, s2, s1, s0 as the output
subtractor4
- Verilog half subtractor module and tests build with made with gates built with expression modules.
read_SRAM
- read from SRAM memory (512kx8)
myCLK
- 24Mhz的频率分成2Mhz的频率。 再由一个I/O口输出。-The frequency of 24Mhz into2Mhz frequency，Again by an I/O port output.
keyboard
- keyboard.c 该文件是总线型键盘的代码，其中包括main主函数以及循环读总线键盘的代码（已加入延时防抖）-keyboard.c
Plus-a-digital-dynamic-scanning
- 通过AT89X52单片机实现数码管动态扫描加1。-Plus a digital dynamic scanning
ADC0804
- 52单片机上ADC0804的驱动程序，通过改变滑动变阻器改变输出值-52 microcontroller ADC0804 driver, change the output value by changing the sliding rheostat
LightCube_Config
- 3d8光立方的板子配置文件，可以直接修改IO口设置-3d8 light cube