搜索资源列表
74HC161
- 74ls161 基于verilog语言的实现 源程序在压缩包的hdl文件夹中-74ls161 language based on the realization of verilog source package in compressed folder hdl
74HC283
- 74ls283 基于verilog语言的实现 源程序在压缩包的hdl文件夹中-74ls161 language based on the realization of verilog source package in compressed folder hdl
Digital-clock
- 数字时钟6位数码管显示。主要器件为74ls48和74ls160 /74ls161。功能：1.显示时、分、秒。2. 可以24小时制或12小时制。3. 具有校时功能-Digital clock six digital tube display. Main components of 74ls48 and 74ls160/74ls161. Features: 1. Shows hours, minutes, seconds. (2) a 24-hour or 12-hour clock. 3 a sc
Maxplus2_74LS161
- 用Maxplus2制作的实现74LS161数字芯片功能，入门级工程。-Maxplus2 made with digital chips to achieve 74LS161 function, entry-level engineering.
m19
- 用VHDL语言实现74LS161的功能，以及用74LS161实现模19计数器的功能(Using VHDL language to achieve the function of 74LS161, as well as using 74LS161 to achieve modulo 19 counter function)