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8位数字频率计
- 数字频率计~ VHDL 实现 可以实现频率的测量和现实的功能 8位-digtal frequency tester (use vhdl) can be used to test frequency (8bit)
8位相位相加乘法器
- 8位相 加乘法器，具有高速，占用资源较少的优点-eight multiplier phase together with high-speed, taking up less resources advantages
一个8位CISC结构的精简CPU
- 一个8位CISC结构的精简CPU，2还提供了编译器-an eight streamline the structure of the CISC CPU, the two also provided compiler
8位大小比较器
- 8位大小比较器的VHDL源代码，Magnitude Comparator VHDL descr iption of a 4-bit magnitude comparator with expansion inputs-eight compared with the size of the VHDL source code, Magnitude Comparator VHDL descr iption of a 4-bit magnitude comparator inputs with e
CH8CH4CH2CH1VHDL 数字电路参考书所有程序8
- CH4CH2CH1VHDL 数字电路参考书所有程序8-CH4CH2CH1VHDL digital circuit reference all proceedings 8
8位加法器
- 8位加法器的原代码,主要内容下载看了就知道-Adder eight of the original code, read the main content downloaded know
8倍频vhdl
- 该文件可用vhdl语言实现时钟8倍频，运行环境可在maxplus2和ise的仿真软件上-the document available VHDL Language 8 clock frequency, the operating environment and ideally maxplus2 simulation software
一个8位处理器结构，源码分析
- 关于一个8位处理器的分析，和源代码，VHDL语言设计，经过测试-on an eight processors, and source code, VHDL design, the test
8-CPU
- 简单的8位CPU，内含PDF文件.可自己查看详细说明-simple eight CPU, containing PDF files. They can check details
FPGA-CPLD_DesignTool(8-9-10)
- FPGA-CPLD_DesignTool(8-9-10)源代码请需要的朋友下载-FPGA-CPLD_DesignTool (8-9-10) requested the source code to their peers in need Friends Download
Crack_Altera_6[1][1].0-9.1
- quartus版本的破解 从6.1至9.0间所有版本-quartus crack version from 6.1 to 9.0 all versions
Crack_QII81_FULL_License
- quartus 8.1 ipcore lic,包含ddr、ddr2、fir、nco-quartus 8.1 ipcore lic, with ddr, ddr2, fir, nco
8-led-VHDL
- 8位流水灯程序设计，跑马灯效果显示，里面是VHDL程序。-8 water lamps program design, which is a VHDL program
80sp1_DSP
- Altera 的DSP Builder 8.0的破解文件-Crack files for dsp builder 8.0
The-Duck
- Crack for Quartus II 8.0
quartusII8.0_crack
- quartusII8.0软件的使用许可，需要学习的朋友可以拿来使用，不要外传，-quartusII8.0 software use license, you must learn from a friend can put to use, not rumor, thank you
tutorial
- quartus ii 6.0版本tutorial文件，在不同的版本中会出现不同的说明介绍，包括6.0/ 7.2/ 8.0。-tutorial for quartus ii 6.0 that illustrate a quiker way to get access of basic feature of the design software
Multiplier_quartus-II8.0
- 在quartus II8.0中实现乘法器，进过仿真验证过的，没有问题。-In quartus II8.0 realization in on time-multiplier, entered the simulation validated, no problem.
3 8
- 用VHDL多种方法实现3-8译码器,元件例化(use VHDL realize 3-8decoder)
3-8译码器VHDL描述
- 在开发板FPGA：Spartan-3E 系列，型号：XC3S500E，封装：FGT320，速度-4；利用XIlinX编程，使用VHDL语言来描述组合逻辑器件3-8译码器(In the FPGA:Spartan-3E development board series, XC3S500E, FGT320, -4 package: speed; the use of XIlinX programming, using VHDL language to describe the combination