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verilog
- 基于Verilog HDL的通信系统设计一书的电子教案，里面有很多例子，大家可以参考一下-Verilog HDL-based communication system design e-book lesson plans, there are many examples we can refer to
ZCYL
- 组成原理课设，设计一个计算N的平方和的微型机，N小于等于8-Composition principle lesson set, design a calculation of the square of N and the microcomputer, N less than or equal 8
8bitcpu_microprogrammed_vhdl
- 八位微程序结构的cpu设计 。 此为课堂设计，欢迎大家参考。 本人联系方式：justin_dengcn@126.com-8 cpu micro-structure of the design process. This is a lesson. please Contact: justin_dengcn@126.com
VHDL_coding
- Powerpoint slides about VHDL coding which teaches in class, inculdes many lesson and also parctice.The ppt file is for learners who want to begin with VHDL.
multiplier
- Moving panes can get confusing, and you may not always obtain the results you expect. Practice moving a pane around, watching the gray outline to see what happens when you drop it in various places. Your layout will be saved when you exit ModelSi
verilog_course_intro
- Verilog简明教案，介绍了verilog几个浅显使用案例，包含源程序，适合本科硬件描述语言学习参考-Verilog concise lesson plans, introduced the verilog several facile use cases, including source code, hardware descr iption language for undergraduate study reference
xilinx_EDK_lesson_ISE12
- Xilinx EDK 系統設計教學 使用ISE 12-Xilinx EDK lesson step by step for ISE 12
TRABALHO4
- It s a sort of problem about sincronous operation using vhdl em DE2. Another homework lesson.
59-50-(2)
- 本人的课设电子时钟VHDL 50秒开始嘀嘀嘀 报警。包含总文件-My lesson an electronic clock tick VHDL 50 seconds to start beeping alarm. Include the total file
decoder2_4
- 一个2—4译码器，我做实验课用的，希望对大家有用-A 2-4 decoder, I did experiment with the lesson, I hope useful
VHDL
- VHDL的电子教案，讲述VHDL语句、语言要素程序结构和仿真等-VHDL electronic lesson plans, tells VHDL language elements statement, a program structure and simulation, etc
CPU
- 东南大学COA下实验设计CPU完整程序，可以在RAM中写程序并可观察各个输出的波形，用于检验。-south-east university COA II the design cpu lesson which you can write your own program in the cpu and also can chack the wave
7_DynDigTub
- FPGA，VHDL语言动态显示一位数码管，使用所有FPGA芯片，课重新分配引脚-FPGA, VHDL language dynamically display a digital tube, all FPGA chip, the lesson reallocate pin! !
FPGAlaguage
- 这是本人在本科期间做的语言系统FPGA课设-This is a language the system FPGA lesson set my undergraduate during
DS18B20
- DS1302Z 读取和设置RTC，时间显示在数码管 在FPGA上实现。课正常使用-[DS1302Z]: read and set the RTC, the time displayed on the digital implemented on FPGA. Lesson normal use
sw_debounce
- Lesson 9 BJ-EPM240学习板实验2——按键消抖实验-Key debounce
work
- 数字系统设计及VHDL课上用的易于混淆的代码-Digital system design and use of the VHDL code lesson is easy to confuse
pwm
- VERILOG 学习第一课，输出一定占空比方波-VERILOG learn the first lesson, a certain duty cycle square wave output
key_xiaodou
- 这是消除抖动源代码的关键，适合刚刚学习vhdl的新手，按键消抖是需要掌握的一课-This is the key to eliminate shaking the source code, suitable for just learning vhdl novice, key to eliminate shaking is a lesson in the need to master
Verilog HDL（第4版）[王金明][电子教案]
- Verilog HDL（第4版）[王金明][电子教案].rar 注意是ppt教案。(Verilog HDL (Fourth Edition) [] [Wang Jinming].rar e-lesson plans note ppt plans.)