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MB
- vhdl秒表程序,从书上看到的例子，试了可以，值得学习。-vhdl stopwatch program, from the book to see examples of the test can be, it is worth learning.
c_xapp260
- xilinx应用指南xapp260的中文翻译版本。利用 Xilinx FPGA 和存储器接口生成器简化存储器接口。本白皮书讨论各种存储器接口控制器设计所面临的挑战和 Xilinx 的解决方案，同时也说明如何使用 Xilinx软件工具和经过硬件验证的参考设计来为您自己的应用（从低成本的 DDR SDRAM 应用到像 667 Mb/sDDR2 SDRAM 这样的更高性能接口）设计完整的存储器接口解决方案。-The use of Xilinx FPGA and Memory Interface Gen
usb_latest.tar
- 用VHDL语言编写的USB 2.0IP核。USB 2.0的传输速率是高速率480 Mb/s，需要再外扩一个PHY。-This is a USB 2.0 compliant core，USB 2.0 allows data transfers of 480 Mb/s. Because of the high interface speed, an external PHY will be required with this core.
flashdemo
- quick test for Cypress RAm (here: 64 MB): VHDL example to test speed and quality of data: write and read process used.
V4LwipUseMb
- 在AVNET的V4FX12开发板上使用MB实现网络的例子，可作为千兆网开发或者其他使用Xilinx芯片的朋友参考。-AVNET board in the development of V4FX12 example of using the MB network can be developed as Gigabit Ethernet or other friends using Xilinx chip reference.
xapp224datarecovery
- Data recovery allows a receiver to extract embedded clock data from an incoming data stream. The receiver usually extracts the data from the incoming clock/data stream and then moves this data into a separate clock domain. Sometimes, the receiver
sdram_controller
- 该模块是一个基于FPGA的SDRAM控制器，该模块有两个接口，一个接口是系统接口，一个连接SDRAM的接口。可以适应不同速度和带宽的SDRAM。-This application note describes the design of a FPGA SDRAM controller.The controller has a system interface on one side and a SDRAM controller for two 16 MB SDRAMs on the other
sssd
- MB CARD FPGA ENTERANCE FOR production lines to inc. process quality and monitoring process step by step phase for better under standing of manufac turing
1
- than dc parameter (saturation current, threshold voltage, etc.) degradation. An electron beam probing was performed on a 64-Mb DRAM chip to detect the influence of gate capacitance variation in dynamic circuit blocks before and after hot-carr