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CORDIC
- 用verilog写的CORDIC算法实现，很适合做超越函数的运算。通常用于实现正弦乘法，或者坐标变换。-The cordic arithmetic implemented by verilog is adapted to exceed function.It is usually used to implement sine multiplication or coordinate tuansform.
anjian
- 按键输入模块（key）： --可编程延时发生器（数字同步机）的前端输入模块：0－9十个数字键按键输入模块原型 --前端模块：消抖 --对i0－i9十个输入端的两点要求： --（1）输入端要保证一段时间的稳定高电平 --（2）不能同时按下两个或多于两个的键 --后级模块：1、编码；2、可变模计数器 --编码模块：8线－4线（0－8 BCD码） --可变模计数器模块：以编码模块输出的32位BCD码为模值-button input module (key) : -- p
alu64_struct
- 六十四位ALU设计源代码，可实现加减，逻辑与，或等多种功能。-64 ALU design source code can be modified to achieve, and logic, or other functions.
lightW
- 一個LCD燈的小程序。不是我寫的。我只負責了調試。適用在ACEXEP1K30QC208-3上。我跑了SIMULATOR，管腳連接標示了。我也下在電路板上試過了，沒有問題。要用到實驗板上的兄弟們把CLK1改到TESTOUT3或者0就好了。綫幫助新手，人人有責。-a small LCD lights procedures. I did not write. I am only responsible for the debugging. Apply in ACEXEP1K30QC208-3 on.
VerilogHDL
- Verilog HDL程序，对硬件开发有兴趣或需要的朋友赶快down下来-Verilog HDL procedures, the development of hardware are interested or needs a friend to see down quickly down
100vhdl例子
- 100vhdl例子 应用于各基础电路或高级电路的基础部分-100vhdl example of the basic circuit used senior circuit or part of the foundation
一个波形发生器和sine波形发生器
- 这是一个典型的正玄波发生器程序和一个任意波形发生器程序，大家可以参考学习，对于vhdl入门还是很有帮助的-This is a typical wave generator Shogen procedures and an arbitrary waveform generator procedures, Members can take a learning portal for VHDL or helpful
quartusii
- 推荐!!!!!学ASIC相当不错的教程!!!!还是可以看看的-recommended !!!!! school ASIC fairly good tutorial! ! ! ! Or can see!
STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD
- 將正在順時針或逆時針旋轉的步進馬達目前角度顯示在ＬＣＭ上。-will is clockwise or anti-clockwise rotation of the stepper motor show in the current perspective on the LCM.
VHDL_Examples_for_education
- VHDL代码编程,集合了众多优秀的实例,胜过任何一本书的例子,作为教学或程序开发中调用非常合适!-VHDL code programming, a combination of a large number of outstanding examples are better than any one book's examples, as a teaching program or call very appropriate!
mux2
- 二进制数据或者频率信号选择器，判决时钟满足低频条件-binary data or frequency signal selectors that the judgment low-frequency clock to meet conditions
OR
- VHDL code for OR gate
CRC-Generator-for-Verilog-or-VHDL
- CRC Generator for Verilog or VHDL-CRC Generator for Verilog or VHDL
or
- or gate implementation in vhdl.
rise-or-fall-detect
- 上升沿、下降沿检测代码,开发语言是verilog HDL，希望对大家有所帮助-rise or fall detect of information and the tool is the software Quartus and the landuage is vrilog HDLthank you for using it hope it will benifit for you
verilog-or-to-led
- 利用verilog语言实现或门实现LED的显示，非常适合初学者来学习这个硬件语言。-Using verilog language or door to achieve the LED display, ideal for beginners to learn the hardware language.
Send-numeric-or-character
- 单片机通过串行口向pc机发送数字或字符，查询法。-Microcontroller through the serial port to the pc machine to send a number or character, the query method.
or
- this the vhdl code for or gate with rtl view and simulations-this is the vhdl code for or gate with rtl view and simulations
Quadruple-2-Input-Exclusive-Or-Gates
- quadruple dual input exclusive or gates
UART-VHDL-Example-Code-for-an-FPGA-or-ASIC-from-n
- UART code using VHDL for FPGA or ASIC