搜索资源列表
NAND01GR3B_VH1
- nand flash NAND01GR3B (st)的仿真模型 （VHDL） 的-nand flash NAND01GR3B (st), the simulation model (VHDL)
M25P32_VG_12_50MHZ
- Serail Nor Flash Memory Model
Splitter
- Splitter file to be used to split altera avalon st video stream into two avalon st streams.
Avalon_Interface
- Avalon,SOPC开发中NIOS II体系结构中使用的总线,很详细的介绍,做NIOS II开发的人员参考-Avalon, SOPC development of the NIOS II architecture used in the bus, a very detailed descr iption, do staff members in NIOS II Development
fft_st
- 用NIOS2核建的FFT工程，能够对输入的数据进行FFT或IFFT变换。-FFT with NIOS2 nuclear construction projects, to input data on FFT or IFFT transform.
avalon
- avalon接口总线标准，的理解，看了之后，会了解avalon-mm和avalon-st-avalon interface bus standards, understanding, looked after, will understand avalon-mm and avalon-st
s25fl040a
- ST S25FL040 Sefial Flash Verilog Model
CoDeSys-programming-Introduction
- codesys编程简介，CoDeSys 是一种功能强大的PLC软件编程工具，它支持IEC61131-3标准IL 、ST、 FBD 、LD、 CFC、 SFC 六种PLC编程语言，用户可以在同一项目中选择不同的语言编辑子程序，功能模块等。-CoDeSys programming Introduction
filter
- Digital filter 1-st level project. Xilnx System Generator sources + verilog sources (PlanAhead project). All docs are in archive. Fully work.
obnar1
- Digital detector (a-type) 1-st level project. Xilnx System Generator sources + verilog sources (PlanAhead project). All docs are in archive. Fully work.
obnar3
- Digital detector (b-type) 1-st level project. Xilnx System Generator sources + verilog sources (PlanAhead project). All docs are in archive. Fully work.
iNEMO-UART-Output
- 意法半导体的惯性传感器套件iNEMO通过串口数据数据的固件，通过J-LINK下载至开发板-iNEMO Toolkit firmwire by ST Ltd. (Data output from UART)
SR
- 基于QUTER的ST器的VHDL语言设计！-Based on the QUTER ST device VHDL language design!
spi
- 一个简易SPI接口程序，地址数据均为一个data输入口，st使能控制开启-A simple SPI interface program, the address data are a data input port
RapidIO_avalonst
- RapidIO：使用Avalon-ST直通接口的实现方法，可以在fpga上实现-rapidio altera
en.SPI_EEPROM_Verilog_models_V10
- spi接口的eeprom模型，型号为st公司m65pxx(The eeprom model of spi interface is st company m65pxx)