搜索资源列表
EX3
- 一个简单的EDA设计，显示4个数码管，根据时钟的频率计数-A simple EDA design, 4 digital tube, according to the frequency of the clock count
ex3
- pll ip核结合七段码 verilog源代码-the pll ip core binding seven-segment code verilog source code
EX3
- 基于FPGA的数码管显示，给刚入门的朋友-FPGA-based digital display, to see friends just getting started. .
ex3
- FPGA控制的电机驱动VHDL代码，可实现正转，反转，启动，停止。并可以实现PWM调速。代码中预留了控制接口，可方便完成上述功能的实现。- The code is for driver based on FPGA. It can realize the function of start, stop, speed adjust.
ex3-6-bank_no_sys
- 银行叫号系统，已经仿真验证，并且在硬件平台测试-Banks have simulation, snarling system, validation, and test the hardware platform