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数字锁相环设计源程序
- PLL是数字锁相环设计源程序, 其中, Fi是输入频率(接收数据), 数字锁相技术在通信领域应用非常广泛，本例用VHDL描述了一个锁相环作为参考，源码已经调试过。编译器synplicty.Fo(Q5)是本地输出频率. 目的是从输入数据中提取时钟信号(Q5), 其频率与数据速率一致, 时钟上升沿锁定在数据的上升和下降沿上；顶层文件是PLL.GDF-digital phase-locked loop PLL design source, in which Fi is the input freque
dll11254
- 数字琐相环DPLL的VERLOG代码，MODELSIM下的工程，有测试文件-digital phase-locked loop DPLL VERLOG code MODELSIM under the projects, a test document
数字锁相环
- PLL是数字锁相环设计源程序, 其中, Fi是输入频率(接收数据), Fo(Q5)是本地输出频率. 目的是从输入数据中提取时钟信号(Q5), 其频率与数据速率一致, 时钟上升沿锁定在数据的上升和下降沿上；顶层文件是PLL.GDF-digital phase-locked loop PLL design source, in which Fi is the input frequency (receive data), Fo (Q5) is the local output frequency.
EP2C20_TEST.rar
- 内含无刷电机驱动VHDL模块，读码盘4倍频模块，并用NIOS核实现简单无刷电机闭环控制。,Brushless motor driver includes VHDL modules, reading frequency module plate 4, and nuclear NIOS simple closed-loop control of brushless motor.
pll.rar
- 模拟锁相环（apll）的一些simulink模型,Analog phase-locked loop (apll) some simulink model
dpll
- 基于Verilog的数字锁相环。包括三个模块，数字鉴相器DPD、数字环路滤波器DLF、数控振荡器 DCO三部分构成-Verilog-based digital PLL. Consists of three modules, the digital phase detector DPD, digital loop filter DLF, digitally controlled oscillator DCO three parts
loop
- 对锁相环路的仿真，二阶环的仿真与分析都可以通过这个文件来到完成-Simulation of PLL, second-order loop simulation and analysis can be completed by the adoption of the document came
PLL
- PLL是数字锁相环设计源程序, 其中, Fi是输入频率(接收数据), Fo(Q5)是本地输出频率. 目的是从输入数据中提取时钟信号(Q5), 其频率与数据速率一致, 时钟上升沿锁定在数据的上升和下降沿上； 顶层文件是PLL.GDF-Digital phase-locked loop PLL is the design source code, which, Fi is the input frequency (receive data), Fo (Q5) is
phase-locked
- 主要是关于锁相环的环路滤波设计与计算，非常经典的-Mainly on the phase-locked loop filter design and calculation, very classic
wtut_sc
- DCM includes a clock delay locked loop used to minimize clock skew for Spartan-3, Virtex-II, Virtex-II Pro, and Virtex-II Pro X devices. DCM synchronizes the clock signal at the feedback clock input (CLKFB) to the clock signal at the input clock
dll_good_2137
- Delay locked loop Exmples
CostasLoop
- costas loop in vhdl -costas loop in vhdl ...
Noise-on-the-PLL-loop-bandwidth
- 一篇介绍的比较详细的关于锁相环噪声与环路带宽的文档-Noise on the PLL loop bandwidth of the document
PLL
- Phase locked loop(PLL) Verilog HDL code
code
- it is the collection of the modules involved inthe design of digital fm.the code coves the key components like numerically controlled oscillator, loop filter, fir filter ,phase detector along with the complete cicuit implementation of the digital fm
loop-HELLO
- 8位数码管循环显示HELLO.采用不同的延时时间，让数码管上HELLO,左右显示时的时间不同-8-bit digital control loop shown HELLO. With different delay time on the digital control HELLO, display different times around
Costas
- 介绍了某直接序列扩频、QPSK调制系统接收通道中四相Costas 载波跟踪环的原理及其基于 DSP+FPGA 的实现-Introduced a direct-sequence spread spectrum, QPSK modulation system, receive path Costas carrier tracking loop four-phase principle and its implementation based on DSP+ FPGA
FIR-LOOP-
- 数字接收机中的FIR滤波器，环形滤波器设计参考,VHDL代码-the FIR filter， loop filter design in a digital receiver,vhdl code
loop
- loop filter IIR for pll Fm demodulator
phase-locked-loop-implementation
- 在FM0数据解码时，利用锁相环生成数据同步时钟信号。文件为锁相环实现。Verilog HDL-When FM0 decoding data using the phase-locked loop generates the data synchronizing clock signal. File for phase-locked loop implementation.Verilog HDL