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2Dfft
- VHDL 关于2DFFT设计程序 u scinode1 ∼ scinode9.vhd: Every SCI node RTL vhdl code. The details can be seen in the following section. u 2dfft.vhd: The top module includes these scinodes and form a 3x3 SCI Torus network, and it support these sub-mo
OpenSpacewire_090406.rar
- SpaceWire节点逻辑，VHDL，希望有帮助,SpaceWire Node logic, can be used widely
bitNode_Behaviora_VHDL
- LDPC码的消息节点（Bitnode）消息更新过程的VHDL语言实现-LDPC code of the message node (Bitnode) news update process of the VHDL language
router_fifo
- 自己写的一个片上网络路由节点的fifo模块，工作频率达到1ghz。-Himself wrote a piece on the network routing node of the fifo module, the work frequency of 1ghz.
router_fifo
- 自己写的一个片上网络路由节点的fifo模块，工作频率达到1ghz。-Himself wrote a piece on the network routing node of the fifo module, the work frequency of 1ghz.
Lab_4_PicoBlaze
- Integrating a picoblaze processor in LabVIEW FPGA by use of CLIP node. Create LabVIEW FPGA Project for Xilinx Spartan 3E starter board. use pBlazIDE to program a psm file that will run on the picoblaze softcore processor.
exp_cpu_vhd
- cpu模型，除了时序和显示模块，有两个warning-A CPU module except downloading parts,such as SHIXU and XIANSHI.This version has 2 warning as below.But functional waveform shows --a right execution of computing. --ZHANG Hongjie 2010.6.11 -- Warning: Inf
round_robin_arbiter
- Round Robin Bus Arbiter for 5-node 8-bit bus
VHDL-node
- VHDL的一些实验代码，其中有4位可逆计数器，4位可逆二进制代码－格雷码转换器设计、序列检测器的设计、基于ROM的正弦波发生器的设计、数字密码锁的设计与实现-Some experiments of VHDL code, which has four reversible counters, four reversible binary code- Gray code converter design, sequence detection Design, ROM-based sine wav
VHDL-node
- VHDL简单程序 包括简单的与门 非门 以及138 等 适合初学者使用-this is VHDL
d4ef13.ZIP
- 基于FPGA的WSNs低功耗节点设计与实现Based on the FPGA WSNs node design and implementation of low power consumption-Based on the FPGA WSNs node design and implementation of low power consumption
8051-IP-Core
- 8051的IP核，可以使用FPGA IP节点导入此IP核，实现单片机的功能。-8051 IP core can be used the FPGA IP node to import this IP core microcontroller functions.