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XC4VLX60MB_Lab5_PROM_ISE91
- XCVLXMB the board Xilinx SRAM_BASED FPGA design is the main element Pieces, SRAM_BASED the FPGA, the design began to verify the results, may experience many changes, this time as long as the JTAG s DOWNLOAD CABLE with the IMPACT software is conti
Process_ECG_Signal
- receipt ECG signal and count pick of signal
fourone
- 四选一数据表决器，ABCD四选一，选择一个输出端口输出所要的电平。实现数据表决-Four data select a voting machine, ABCD four-pick one, choose an output port to the output level. Data division
manchester_verilog
- This design is targeted to the XCR3064XL-7VQ100C CoolRunner CPLD. This is a 3V, 64 macrocell device in a 100 VQFP package. The fitter was allowed to pick the pin-out for the device.
manchester_vhdl
- This design is targeted to the XCR3064XL-7VQ100C CoolRunner CPLD. This is a 3V, 64 macrocell device in a 100 VQFP package. The fitter was allowed to pick the pin-out for the device.
uart_verilog
- The UART design was designed from a standard uart function with a read/write microprocessor interface. It includes standard framing error, parity control and overrun detection. This design is targeted to the XCR3128XL-7VQ100C CoolRunner CPLD. This
uart_vhdl
- The UART design was designed from a standard uart function with a read/write microprocessor interface. It includes standard framing error, parity control and overrun detection. This design is targeted to the XCR3128XL-7VQ100C CoolRunner CPLD. This
ps2_keyboard_test
- FPGA通过ps2接收键盘数据，然后把接收到的字母A到Z键值转换相应的ASII码，通过串口发送到PC机上。需要接键盘，还要用调试助手，下载程序后，在键盘上按下一个键，比如A，则在PC调试助手上可看到A-FPGA received by ps2 keyboard data, and then received the letters A through Z keys to convert the corresponding ASII code, sent through the serial po
di4
- 1、 用16*16点阵的发光二极管逐行扫描显示“一”字。 2、 输入为四位二进制矢量。 3、 采用行列扫描的方法，用四位二进制做行选信号（总共16列），如选中第一行，则扫描第一行之中哪些行是高电平（1），哪些行是低电平（0） 为高电平的则点亮，为低电平的不亮。 4、 注意扫描频率的设置，扫描频率足够快，才能动态扫描“一”字。 5、 程序由行扫描模块和显示模块构成。 行扫描模块输入为一个时钟信号和重置信号，输出为4位二进制（用sel表示）行选信号，用来选中行，进行扫描。 显
wu2
- 1、 用16*16点阵的发光二极管逐行扫描显示“一”字。 2、 输入为四位二进制矢量。 3、 采用行列扫描的方法，用四位二进制做行选信号（总共16列），如选中第一行，则扫描第一行之中哪些行是高电平（1），哪些行是低电平（0） 为高电平的则点亮，为低电平的不亮。 4、 注意扫描频率的设置，扫描频率足够快，才能动态扫描“一”字。 5、 程序由行扫描模块和显示模块构成。 行扫描模块输入为一个时钟信号和重置信号，输出为4位二进制（用sel表示）行选信号，用来选中行，进行扫描。
ps2_keyboard_test
- FPGA通过ps2接收键盘数据，然后把接收到的字母A到Z键值转换相应的ASII码，通过串口发送到PC机上。 实验时，需要接键盘，还要用调试助手，下载程序后，在键盘上按下一个键，比如A，则在PC调试助手上可看到A -FPGA receives data via the keyboard ps2, and then received the letters A through Z keys corresponding conversion ASII code sent to the PC v
Code-speed-adjustment-circuit
- 基于同步的数字 复接系统, 即输入的数据码流速率相同。若各 支路 的数 据码 流速 率不 同, 则 不能 直接 进行 复接, 因为复接合成后的数字信 号流, 在 接收端是无法分接恢复成原来的信号的, 为此在复接 前要使各支路数码率同步, 我们可以在设计的同步数字复接系 统前方加一码速调整单元, 以调整各支路的速码率使其同步, 并在分接 后再经过码速调整恢复为原来的速率。 -Based on the synchronous digital multiplex system, namely th
syn_rst
- 指定同步复位时， always的敏感表中仅有时钟沿信号，仅仅当时钟沿采到同步复位的有效电平时，才会在时钟沿到达时刻进行复位操作-Specifies synchronous reset, always sensitive to the table is just a clock edge signal only when the clock along to pick active level synchronous reset, the clock edge arrival time will