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uart from opencores
- 用VHDL实现串口 可以实现与pc机的通信 收发 中断都可以 效果比较好-VHDL implement serial port, it can communicate with pc, it can accept and send message, and it can be interrupted.
Automat
- 设计一个自动售货机控制程序，它的投币口每次可以投入1元、2元、5元，且规定投入1元或2元后不得再投入5元。当投入总值等于或超过设定值（4元），售货机就自动送出货物并找回多余的钱。-design a vending machine control procedures, it can slot into each one yuan, the two yuan, 5 billion there are provisions into one yuan or two yuan may re-enter
VHDL_infrared_telecontrol_design
- Infrared telecontrol design based on the the VHDL includes the mode of infrared send,receive mode,key code mode,ringing mode and so on.
system 完成远程通信的整体任务
- Verilog，QuartusII可正确运行，可下载到FPGA上，完成远程通信的整体任务，PC发数据，键盘输入运算符与运算数计算将结果显示在数码管上并返回给PC机，需异步串口调试软件-Verilog, QuartusII run correctly, can be downloaded to the FPGA, to complete the overall task of remote communication, PC send data, keyboard operators and op
SPIsend.rar
- Verilog HDL的程式，上網找到SPI程式， vspi.v這程式相當好用可用來接收與傳送SPI，並且寫了一個傳輸信號測試，spidatasent.v這程式就是傳送的資料，分別為00 66... 01 77...... 02 55這樣的資料，並透過MAX+PULS II軟體進行模擬，而最外層的程式是test_createspi.v！,Verilog HDL programs, Internet find SPI program, vspi.v this very useful progra
uart8.zip
- 使用Libero提供的异步通信IP核实现UART通信，并附带仿真程序。UART设置为1位开始位，8位数据位，1位停止位，无校验。且UART发送自带2级FIFO缓冲，占用FPGA面积很小。,Libero provided the use of asynchronous communication IP core implementation UART communications, and incidental simulation program. UART is set to 1 to sta
FIFO_EMIF.rar
- 实现FPGA通过EMIF总线给DSP定期发送数据的功能,FPGA implementation through the EMIF bus regularly send data to the DSP function
LM3SUARTSENDFIFO
- LM3S系列UART例程：发送FIFO触发中断原理-LM3S Series UART routines: Send principle of FIFO trigger interrupt
PC_WR_EEPROM
- 利用altera公司的FPGA使用verilog语言实现对EEPROM的读和写的功能 利用串口发送数据-Altera FPGA verilog language to achieve the serial port to send data to the EEPROM read and write
RF24L01yaokong
- MSP430F149—nRF24L01的全双工通信程序，发送端通过按键发送键值，接受端接受并用LCD显示。-MSP430F149-nRF24L01 full-duplex communication process, sender to send keys through the key, the receiving end to accept and use the LCD display.
FPGA_UART
- FPGA串口实现。 发送和接受数据功能代码-FPGA serial interface. Send and receive data function code
UART
- 自己实用Verilog编写的UART程序，1位开始位，8位数据位，1位停止位，本测试程序配置完管脚后，实用串口大师发送数据，则返回数据为发送数据+1-Verilog prepared their own UART practical procedures to start a bit, 8 data bits, 1 stop bit, the test procedure End pin configuration, the utility serial Master to send data,
recuart_50m
- 本代码功能为实现接收PC发送的串口数据功能 程序通过quartusII 8.1编译，使用verilog语言编写。 可在彬杰科技*BJTECH公司基于altera epm240的开发板上验证。 （开发板网址http://item.taobao.com/auction/item_detail-0db1-69fe7069aa3ba544abf783bc4427b377.htm） 有需要的朋友可以下载参考-The code functions to achieve the receivi
ps2键盘接口
- 基于Xilinx Spartan3E的ps/2键盘接口，能够把键值传送到FPGA上并在LCD上显示-Xilinx Spartan3E based on the ps/2 keyboard interface, be able to send to the FPGA on the keys and LCD display
uart
- uart send resive module
send
- 串口发送子程序verilog 串口发送子程序verilog -uart send verilog
send
- 采用vhdl语言编程，实现异步串行通信的发送自己定义的通信协议格式-Using vhdl language programming, asynchronous serial communication to send their own communication protocol format definition
Send-numeric-or-character
- 单片机通过串行口向pc机发送数字或字符，查询法。-Microcontroller through the serial port to the pc machine to send a number or character, the query method.
Fix-data-send-UART
- Fix data UART send and receive verilog codes.
uart_rx
- Verilog实现的RS232发送和接收程序，有完成的verilog代码，testbench等。(UART send and receive verilog code, including verilog source code, testbench etc.)