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Splitter
- Splitter file to be used to split altera avalon st video stream into two avalon st streams.
splitbaseplateFFT
- 分裂基FFT的实现,花钱下的资料，大家都来-split baseplate fft
splitscreen
- 分屏算法，将一个屏分为两个屏，两个屏的像素等于一个屏的像素-splitscreen algorithm，used to split one screen into two screen
success01
- 1、可以分屏显示时、分、秒，可用数码管的小数点“.”代替时、分、秒的分隔符“：”，分屏显示是指由于数码管只有4个，不能同时显示时、分、秒，但可以只显示时、分，或只显示分、秒，通过按键来切换这两种显示方式； 2、可设置时钟的开始时间。设置时，相应的数码管要闪烁，指示当前设置的位置（内容）； 3、具有闹铃功能，可以设定闹铃时间。闹铃时间到，LED闪烁进行指示。 -1, can be split-screen display hours, minutes, seconds, used di
mem_wb
- 采用Verilog编写的存储器，使用lpm_ram_dq模拟主存。主要内容为实现了存储器的奇偶分体，使得该存储器可以进行字或字节的读写操作。-Written by Verilog memory, use lpm_ram_dq simulated main memory. The main content of the memory parity split making the memory word or byte read and write operations.
CoreFIR_RTL-3.0
- actelIP核 的fircore Core Generator – Executable File Outputs Run-Time Library (RTL) Code and Testbench Based on Input Parameters – Self-Checking – Executable Tests Generated Output against Algorithm • Distributed Arithmetic (DA) Algori
top6
- fpga2分屏代码，实现dvi输入视频信号，双路dvi输出视频信号，完成1分2-fpga2 split-screen code to achieve dvi input video signal, dual dvi output video signal, completed 1 of 5
implentation of split radix fft through verilog
- this is a verilog code fro implentation of split radix fft
counter
- 一个100MHZ的时钟信号经过分频器得到1HZ信号，然后输入到三位计数器中，计数器的输出在相应的FPGA上的LED灯上展示。该程序主要包含四部分：测试文件、顶层文件、分屏器模块和计数器模块。-100MHZ clock signal through a divider to get 1HZ signal, and then input to the three counters, the output of the counter displayed on the corresponding LE
mouse_kit
- 实现难度可调（6级，速度不同）的简单打地鼠游戏。开发板上的led灯代表地鼠，按键代表锤子。此程序代码可直接执行，适合初学者VHDL入门。 源码中，divider为分屏器；key_scan为按键扫描；random产生随机数；music为背景音乐播放模块；manage为主程序模块。-Adjustable implementation difficulty (6 level, different speeds) simple whack-a-mole game.The led lights on
Keyer
- Video Keyer supporting Luminance key, Self key, Matt key and Split key
VERILOG-Simulation
- This VERILOG simulation example shows a 16 bit group ripple adder circuit for FPGA. The netlabel is used to split 16 bit bus to four 4 bit bus and connect them to four 4 bit adder. The result is joined to a 16 bit bus using netlabel. The Simulation c